{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T04:05:12Z","timestamp":1742184312853,"version":"3.38.0"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2003,7,1]],"date-time":"2003-07-01T00:00:00Z","timestamp":1057017600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2003,7]]},"DOI":"10.1109\/tc.2003.1214337","type":"journal-article","created":{"date-parts":[[2003,7,23]],"date-time":"2003-07-23T15:30:38Z","timestamp":1058974238000},"page":"881-895","source":"Crossref","is-referenced-by-count":2,"title":["Variable instruction set architecture and its compiler support"],"prefix":"10.1109","volume":"52","author":[{"given":"J.","family":"Liu","sequence":"first","affiliation":[]},{"given":"F.","family":"Chow","sequence":"additional","affiliation":[]},{"given":"T.","family":"Kong","sequence":"additional","affiliation":[]},{"given":"R.","family":"Roy","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/ISCA.2000.854391"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/378239.378460"},{"year":"2002","article-title":"The ARCtangent-A5 Processor\u2014A Technical Summary","key":"ref3"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/FPGA.1995.477415"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1145\/378239.378459"},{"volume-title":"CGN16100 Network Processor User Manual","year":"2002","key":"ref6"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/MICRO.1992.697002"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/ICCD.1994.331903"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/MICRO.1997.645810"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1145\/277044.277185"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1147\/rd.426.0807"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1145\/298865.298867"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1145\/349214.349233"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/DAC.2002.1012590"},{"volume-title":"Computer Architecture: A Quantitative Approach","year":"2003","author":"Hennessy","key":"ref15"},{"key":"ref16","article-title":"The SGI Pro64 Compiler Infrastructure","author":"Gao","year":"2000","journal-title":"Tutorial, Int\u2019l Conf. Parallel Architectures and Compilation Techniques"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/12.29469"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1145\/349299.349318"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/TC.1981.1675826"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/icpp.1997.622580"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1145\/502175.502178"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/PACT.2000.888354"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1007\/3-540-44905-1_31"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1002\/9781118627372"},{"volume-title":"Model Building in Mathematical Programming","year":"1993","author":"Williams","key":"ref25"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1093\/comjnl\/8.3.250"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1145\/155183.155190"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/43.275355"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1145\/238997.239002"},{"year":"1955","author":"Jackson","article-title":"Scheduling a Production Line to Minimize Maximum Tardiness","key":"ref30"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/PACT.1998.727188"},{"key":"ref32","first-page":"599","article-title":"Symmetry Breaking during Search in Constraint Programming","volume-title":"Proc. European Conf. Artificial Intelligence (ECAI) 2000","author":"Smith"},{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1007\/3-540-45578-7_53"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1109\/TC.1972.5008918"},{"doi-asserted-by":"publisher","key":"ref35","DOI":"10.1109\/71.372778"},{"volume-title":"Proc. Network Processor Conf.","author":"Kong","article-title":"Cognigine C Compiler: Harnessing the Power of the CGN16100 Network Processor","key":"ref36"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1109\/PACT.2002.1106004"},{"doi-asserted-by":"publisher","key":"ref38","DOI":"10.1145\/581630.581633"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/27304\/01214337.pdf?arnumber=1214337","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:23:14Z","timestamp":1742098994000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1214337\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,7]]},"references-count":38,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2003,7]]}},"URL":"https:\/\/doi.org\/10.1109\/tc.2003.1214337","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2003,7]]}}}