{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T04:07:49Z","timestamp":1742184469809,"version":"3.38.0"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2003,9,1]],"date-time":"2003-09-01T00:00:00Z","timestamp":1062374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2003,9]]},"DOI":"10.1109\/tc.2003.1228514","type":"journal-article","created":{"date-parts":[[2003,9,11]],"date-time":"2003-09-11T19:12:07Z","timestamp":1063307527000},"page":"1196-1209","source":"Crossref","is-referenced-by-count":3,"title":["Efficient minimization and manipulation of linearly transformed binary decision diagrams"],"prefix":"10.1109","volume":"52","author":[{"given":"W.","family":"Gunther","sequence":"first","affiliation":[]},{"given":"R.","family":"Drechsler","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/iccad.1995.480018"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597155"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.509865"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643609"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3596-3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/12.73590"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1992.205890"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/196244.196444"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1006\/inco.1995.1167"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/12.324545"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(94)00078-W"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.486278"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48340-3_23"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1999.760024"},{"key":"ref15","first-page":"167","article-title":"Minimization of Free BDDs Using Evolutionary Techniques","volume-title":"Proc. Int\u2019l Workshop Logic Synthesis","author":"G\u00fcnther"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217583"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/aspdac.1997.600304"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/S0020-0190(00)00083-1"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/43.845077"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580029"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref22","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2892-7","volume-title":"Binary Decision Diagrams\u2014Theory and Implementation","author":"Drechsler","year":"1998"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114826"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0031824"},{"volume-title":"CUDD: CU Decision Diagram Package Release 2.3.0","year":"1998","author":"Somenzi","key":"ref25"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114828"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/37888.37941"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/43.833206"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2866-8"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19960789"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-59175-3_82"},{"article-title":"Logic Synthesis and Optimization Benchmarks User Guide","year":"1991","author":"Yang","key":"ref32"},{"key":"ref33","first-page":"663","article-title":"A Neutral Netlist of 10 Combinational Circuits and a Target Translator in Fortran","volume-title":"Proc. Int\u2019l Symp. Circuits and Systems, special session on ATPG and fault simulation","author":"Brglez"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/27555\/01228514.pdf?arnumber=1228514","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T05:03:34Z","timestamp":1742101414000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1228514\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,9]]},"references-count":33,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2003,9]]}},"URL":"https:\/\/doi.org\/10.1109\/tc.2003.1228514","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2003,9]]}}}