{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:32:11Z","timestamp":1742387531181,"version":"3.38.0"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2004,2,1]],"date-time":"2004-02-01T00:00:00Z","timestamp":1075593600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2004,2]]},"DOI":"10.1109\/tc.2004.1261823","type":"journal-article","created":{"date-parts":[[2004,2,24]],"date-time":"2004-02-24T21:01:05Z","timestamp":1077656465000},"page":"114-125","source":"Crossref","is-referenced-by-count":13,"title":["Thread partitioning and value prediction for exploiting speculative thread-level parallelism"],"prefix":"10.1109","volume":"53","author":[{"given":"P.","family":"Marcuello","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Gonzalez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Tubella","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742784"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765940"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995697"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1999.807404"},{"key":"ref5","first-page":"109","article-title":"Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading","volume-title":"Proc. Int\u2019l Conf. Parallel Architectures and Compilation Techniques","author":"Dubey"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1992.753304"},{"article-title":"Speculative Execution Based on Value Prediction","year":"1996","author":"Gabbay","key":"ref7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/bfb0002857"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1998.650559"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291020"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1996.537165"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/277830.277852"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.5821\/dissertation-2117-93291"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305214"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809461"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2002.995698"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744311"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1999.807576"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645805"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566447"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566465"},{"article-title":"Implementations of Context-Based Value Predictors","year":"1997","author":"Sazeides","key":"ref23"},{"key":"ref24","first-page":"414","article-title":"Multiscalar Processors","volume-title":"Proc. Int\u2019l Symp. Computer Architecture","author":"Sohi"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/178243.178260"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995699"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1998.650541"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991129"},{"key":"ref29","first-page":"392","article-title":"Simultaneous Multithreading: Maximizing On-Chip Parallelism","volume-title":"Proc. Int\u2019l Symp. Computer Architecture","author":"Tullsen"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1996.552553"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264119"},{"key":"ref32","article-title":"Compiling for the Multiscalar Architecture","volume-title":"Univ. of Wisconsin-Madison","author":"Vijaykumar","year":"1998"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645819"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953302"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/28203\/01261823.pdf?arnumber=1261823","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:45:24Z","timestamp":1742100324000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1261823\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,2]]},"references-count":34,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2004,2]]}},"URL":"https:\/\/doi.org\/10.1109\/tc.2004.1261823","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2004,2]]}}}