{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:48:01Z","timestamp":1759146481493},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2004,2,1]],"date-time":"2004-02-01T00:00:00Z","timestamp":1075593600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2004,2]]},"DOI":"10.1109\/tc.2004.1261827","type":"journal-article","created":{"date-parts":[[2004,2,24]],"date-time":"2004-02-24T21:01:05Z","timestamp":1077656465000},"page":"168-186","source":"Crossref","is-referenced-by-count":37,"title":["Power-aware branch prediction: characterization and design"],"prefix":"10.1109","volume":"53","author":[{"given":"D.","family":"Parikh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Skadron","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yan Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Stan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","author":"turley","year":"1998","journal-title":"ColdFire Doubles Performance with v4"},{"key":"ref32","first-page":"68","article-title":"Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures","author":"tang","year":"2001","journal-title":"Proc 2001 Int'l Conf Computer Design"},{"key":"ref31","year":"2000","journal-title":"SPEC CPU2000 Benchmarks"},{"key":"ref30","first-page":"29","author":"song","year":"1997","journal-title":"UltraSparc-3 aims at MP servers"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997880"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/123465.123475"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569645"},{"key":"ref10","year":"1995","journal-title":"Alpha 21164 Microprocessor Hardware Reference Manual"},{"key":"ref11","article-title":"Using IPC Variation in Workload with Externally Specified Rates to Reduce Power-Consumption","author":"ghiasi","year":"2000","journal-title":"Proc Workshop Complexity-Effective Design"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1145\/313817.313860","article-title":"Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation","author":"ghose","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.535411"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"122","DOI":"10.1145\/279361.279376","article-title":"Confidence Estimation for Speculation Control","author":"grunwald","year":"1998","journal-title":"Proc 25th Ann Int'l Symp Computer Architecture"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566423"},{"key":"ref16","first-page":"442","article-title":"Applying Decay Strategies to Branch Predictors for Leakage Energy Savings","author":"hu","year":"2002","journal-title":"Proc 2002 Int'l Conf Computer Design"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1109\/MICRO.2000.898059","article-title":"The Impact of Delay on the Design of Branch Predictors","author":"jim\ufffdnez","year":"2000","journal-title":"Proc 33rd Ann IEEE\/ACM Int'l Symp Microarchitecture"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1998.727028"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645809"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2000.888344"},{"key":"ref3","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref27","article-title":"Speculative Updates of Local and Global Branch History: A Quantitative Analysis","volume":"2","author":"skadron","year":"2000","journal-title":"J Instruction-Level Parallelism"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"287","DOI":"10.1145\/223982.224439","article-title":"Next cache line and set prediction","author":"calder","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288166"},{"key":"ref29","first-page":"135","article-title":"A Study of Branch Prediction Strategies","author":"smith","year":"1981","journal-title":"Proc Eighth Ann Int'l Symp Computer Architecture"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476833"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1996.501190"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937451"},{"key":"ref9","year":"1994","journal-title":"DECchip 21064\/21064A Alpha AXP Microprocessors Hardware Reference Manual"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809463"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694769"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/143365.143490"},{"key":"ref21","author":"mcfarling","year":"1993","journal-title":"Combining Branch Predictors"},{"key":"ref24","author":"parikh","year":"2001","journal-title":"Power Issues Related to Branch Prediction"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995713"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742787"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2000.824355"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/28203\/01261827.pdf?arnumber=1261827","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,12]],"date-time":"2024-01-12T14:39:50Z","timestamp":1705070390000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1261827\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,2]]},"references-count":37,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2004,2]]}},"URL":"https:\/\/doi.org\/10.1109\/tc.2004.1261827","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2004,2]]}}}