{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:33:31Z","timestamp":1772724811935,"version":"3.50.1"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2004,10,1]],"date-time":"2004-10-01T00:00:00Z","timestamp":1096588800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2004,10]]},"DOI":"10.1109\/tc.2004.79","type":"journal-article","created":{"date-parts":[[2004,8,31]],"date-time":"2004-08-31T23:19:17Z","timestamp":1093994357000},"page":"1244-1259","source":"Crossref","is-referenced-by-count":21,"title":["Late allocation and early release of physical registers"],"prefix":"10.1109","volume":"53","author":[{"given":"T.","family":"Monreal","sequence":"first","affiliation":[]},{"given":"V.","family":"Vinals","sequence":"additional","affiliation":[]},{"given":"J.","family":"Gonzalez","sequence":"additional","affiliation":[]},{"given":"A.","family":"Gonzalez","sequence":"additional","affiliation":[]},{"given":"M.","family":"Valero","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937428"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991122"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2000.898083"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995719"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176236"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2000.824345"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/377792.377854"},{"key":"ref9","first-page":"316","article-title":"Multiple-Banked Register File Architectures","volume-title":"Proc. 27th Ann. Int\u2019l Symp. Computer Architecture (ISCA \u201900)","author":"Cruz"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645806"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1996.501172"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1998.650557"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HIPC.1997.634516"},{"issue":"4","key":"ref14","first-page":"9","article-title":"Intel\u2019s P6 Uses Decoupled Superscalar Design","volume-title":"Microprocessor Report","volume":"9","author":"Gwennap","year":"1995"},{"issue":"13","key":"ref15","first-page":"1","article-title":"Mips r12000 to Hit 300 Mhz","volume-title":"Microprocessor Report, Micro Design Resources","volume":"11","author":"Gwennap","year":"1997"},{"key":"ref16","article-title":"The Microarchitecture of the Pentium 4 Processor","author":"Hinton","year":"2001","journal-title":"Intel Technology J. Q1"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/30350.30353"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/356654.356657"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003562"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CMPCON.1995.512398"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/71.798316"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645804"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809456"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2002.1040854"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1993.282756"},{"key":"ref27","article-title":"Wave Pipelining of High Performance CMOS Static Ram","author":"Nowka","year":"1994"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176248"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/2.612249"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2000.824366"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/40.877952"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/327070.327125"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232993"},{"key":"ref35","first-page":"392","article-title":"Simultaneous Multithreading: Maximizing On-Chip Parallelism","volume-title":"Proc. 22nd Ann. Int\u2019l Symp. Computer Architecture (ISCA \u201995)","author":"Tullsen"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/106972.106991"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1996.552666"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/40.491460"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2000.898065"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/12.910816"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/29358\/01327576.pdf?arnumber=1327576","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T05:11:14Z","timestamp":1742188274000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1327576\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,10]]},"references-count":40,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2004,10]]}},"URL":"https:\/\/doi.org\/10.1109\/tc.2004.79","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2004,10]]}}}