{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T21:39:35Z","timestamp":1762033175436,"version":"3.37.3"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Science Foundation of China","doi-asserted-by":"publisher","award":["61379040","61272131","61202053","61222204","61221062"],"award-info":[{"award-number":["61379040","61272131","61202053","61222204","61221062"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004608","name":"Jiangsu Provincial Natural Science Foundation","doi-asserted-by":"publisher","award":["SBK201240198"],"award-info":[{"award-number":["SBK201240198"]}],"id":[{"id":"10.13039\/501100004608","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Strategic Priority Research Program of CAS","award":["XDA06010403"],"award-info":[{"award-number":["XDA06010403"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2015,5,1]]},"DOI":"10.1109\/tc.2014.2315628","type":"journal-article","created":{"date-parts":[[2014,4,9]],"date-time":"2014-04-09T18:01:58Z","timestamp":1397066518000},"page":"1296-1310","source":"Crossref","is-referenced-by-count":20,"title":["Architecture Support for Task Out-of-Order Execution in MPSoCs"],"prefix":"10.1109","volume":"64","author":[{"given":"Chao","family":"Wang","sequence":"first","affiliation":[{"name":"Department of Computer Science, Hefei, Anhui, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xi","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Hefei, Anhui, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junneng","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Science and Technology of China, Hefei 230027, Anhui, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Chen","sequence":"additional","affiliation":[{"name":"State Key Lab of CARCH, CAS, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yunji","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Science and Technology of China, Hefei 230027, Anhui, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuehai","family":"Zhou","sequence":"additional","affiliation":[{"name":"Suzhou Institute of University of Science and Technology of China, Suzhou 215123, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ray C.C.","family":"Cheung","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"66","article-title":"The hyperprocessor: A template\n system-on-chip architecture for embedded multimedia applications","author":"karim","year":"0","journal-title":"Proc Workshop Appl Specific Processors"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1147\/rd.111.0025"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2004.55"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804107"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.39"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.15"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555763"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.27"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749719"},{"key":"ref34","first-page":"413","article-title":"DBAR: An efficient routing algorithm to\n support multiple concurrent applications in networks-on-chip","author":"sheng ma","year":"0","journal-title":"Proc 38th Int Symp on Comput Architect"},{"key":"ref10","first-page":"213","article-title":"The Cedar system and an initial\n performance study","author":"kuck","year":"0","journal-title":"Proc 25 Years Int Symp Comput Archit (Sel Papers)"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/MM.2004.1","article-title":"A multilevel computing architecture for\n embedded multimedia applications","volume":"24","author":"faraydon","year":"2004","journal-title":"IEEE Micro"},{"year":"0","key":"ref40"},{"key":"ref12","first-page":"414","article-title":"Multiscalar processors","author":"sohi","year":"0","journal-title":"Proc Int Symp Comput Archit"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645805"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"589","DOI":"10.1147\/rd.494.0589","article-title":"Introduction to the Cell multiprocessor","volume":"49","author":"kahle","year":"2005","journal-title":"IBM J Res Develop"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/40.848474"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253203"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.19"},{"key":"ref19","first-page":"89","article-title":"Task superscalar: An out-of-order task\n pipeline","author":"deng","year":"0","journal-title":"Proc 43rd Annu IEEE\/ACM Int Symp Microarchit"},{"key":"ref28","first-page":"172","article-title":"A high-performance microarchitecture with\n hardware-programmable functional units","author":"razdan","year":"0","journal-title":"Proc 27th Annu Int Symp Microarchit"},{"year":"0","author":"group","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564773"},{"year":"0","author":"board","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1177\/1094342009106195"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329185"},{"key":"ref5","first-page":"207","article-title":"Cilk: An efficient multithreaded runtime\n system","author":"robert","year":"0","journal-title":"Proc 5th ACM SIGPLAN Symp Principles Practice Parallel Program"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155628"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/561672"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19595-2_13"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1978542.1978558"},{"key":"ref20","first-page":"201","article-title":"A distributed, simultaneously multi-threaded\n (SMT) processor with clustered scheduling windows for scalable DSP performance","volume":"50","author":"mladen","year":"2008","journal-title":"J Signal Process Syst - Special Issue Embedded Comput Syst DSP"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1941553.1941563"},{"key":"ref21","first-page":"137","article-title":"Flexible and efficient instruction-grained\n run-time monitoring using on-chip reconfigurable fabric","author":"mladen","year":"0","journal-title":"in Proc 43rd Annu IEEE\/ACM Int Symp Microarchit 2010"},{"key":"ref24","first-page":"17","article-title":"Ease of use with concurrent collections\n (CnC)","author":"knobe","year":"0","journal-title":"Proc First USENIX Conf Hot Topics Parallelism"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/SCC.2011.26"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1535\/itj.1104.07"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2007","author":"hennessy","key":"ref41"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624600"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821545"},{"year":"0","key":"ref43"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7079452\/06785969.pdf?arnumber=6785969","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,15]],"date-time":"2022-06-15T14:33:00Z","timestamp":1655303580000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6785969\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5,1]]},"references-count":43,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tc.2014.2315628","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2015,5,1]]}}}