{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,1,24]],"date-time":"2024-01-24T01:01:28Z","timestamp":1706058088140},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2014]]},"DOI":"10.1109\/tc.2014.2339813","type":"journal-article","created":{"date-parts":[[2014,7,16]],"date-time":"2014-07-16T18:55:08Z","timestamp":1405536908000},"page":"1-1","source":"Crossref","is-referenced-by-count":3,"title":["Ensuring cache reliability and energy scaling at near-threshold voltage with Macho"],"prefix":"10.1109","author":[{"given":"Tayyeb","family":"Mahmood","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seokin","family":"Hong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soontae","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1543753.1543757"},{"key":"ref11","first-page":"171","article-title":"A 160 MV, fully differential, robust Schmitt trigger based sub-threshold SRAM","author":"kulkarni","year":"0","journal-title":"Proc Int Symp Low Power Electron Design"},{"key":"ref12","first-page":"469","article-title":"An integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"li","year":"0","journal-title":"Proc 42nd Annu IEEE\/ACM Int Symp Microarchit"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.57"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2038698.2038714"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522347"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.28"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2013.6575314"},{"key":"ref19","author":"rausand","year":"2003","journal-title":"System reliability theory Models statistical methods and applications"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669127"},{"key":"ref6","first-page":"292","article-title":"Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS","author":"chen","year":"0","journal-title":"Proc 23rd IEEE VLSI Test Symp"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007170"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669126"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749758"},{"key":"ref9","first-page":"268","article-title":"The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies","author":"gerosa","year":"0","journal-title":"Proc IEEE Int Conf Comput Design"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000118"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref22","author":"weste","year":"2010","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2055589"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref23","first-page":"203","author":"wilkerson","year":"0","journal-title":"Proc 35th Int Symp Comput Archit"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7104223\/06857329.pdf?arnumber=6857329","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:57Z","timestamp":1642005717000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6857329\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/tc.2014.2339813","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2014]]}}}