{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:07:48Z","timestamp":1759147668639},"reference-count":53,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2015,7,1]],"date-time":"2015-07-01T00:00:00Z","timestamp":1435708800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2015,7,1]]},"DOI":"10.1109\/tc.2014.2346208","type":"journal-article","created":{"date-parts":[[2014,8,7]],"date-time":"2014-08-07T18:35:33Z","timestamp":1407436533000},"page":"1940-1953","source":"Crossref","is-referenced-by-count":5,"title":["Interleaving in Systolic-Arrays: A Throughput Breakthrough"],"prefix":"10.1109","volume":"64","author":[{"given":"Giovanni","family":"Causapruno","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Vacca","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mariagrazia","family":"Graziano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maurizio","family":"Zamboni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"763","article-title":"A technology aware magnetic QCA NCL-HDL architecture","author":"graziano","year":"0","journal-title":"Proc Int Conf Nanotechnol"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2012.2207965"},{"key":"ref33","article-title":"Limits of CMOS technology scaling and technologies beyond-CMOS","author":"rairigh","year":"2005"},{"key":"ref32","first-page":"1187","article-title":"Mapping multiple algorithms into a reconfigurable systolic array","author":"jin","year":"0","journal-title":"Proc Canadian Conf Elect Comput Eng"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4630032"},{"key":"ref30","article-title":"Protein alignment systolic array throughput optimization","author":"causapruno","year":"2014","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2261824"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2012.05.022"},{"key":"ref35","first-page":"62","article-title":"Molecular electronics-From structure to circuit dynamics","author":"liu","year":"0","journal-title":"Proc 6th IEEE Conf Nanotechnol"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/81.873875"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/76.97977"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"413","DOI":"10.1109\/76.564119","article-title":"Unified systolic arrays for computation of the DCT\/DST\/DHT","volume":"7","author":"pan","year":"1997","journal-title":"IEEE Trans Circuits Syst Video Technol"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311337"},{"key":"ref2","article-title":"10,000-core linux supercomputer built in Amazon cloud","author":"brodkin","year":"2011","journal-title":"Netw World"},{"key":"ref1","author":"kung","year":"1987","journal-title":"VLSI Array Processors"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647586"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/78.757223"},{"key":"ref21","author":"kung","year":"1978","journal-title":"Systolic arrays for VLSI"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/78.80779"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/78.165667"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/78.193224"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/76.678625"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675922"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.21"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2013.6563320"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2253118"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.234"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2211903"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"160","DOI":"10.1145\/2765491.2765520","article-title":"ToPoliNano: Nanoarchitectures design made real","author":"frache","year":"2012","journal-title":"2012 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH) NANOARCH"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2118229"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1016\/j.micpro.2010.09.006","article-title":"A NOC-based hybrid message-passing\/shared-memory approach to CMP design","volume":"35","author":"r","year":"2011","journal-title":"Microprocess Microsyst"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"49","DOI":"10.1088\/0957-4484\/4\/1\/004","article-title":"Quantum cellular automata","volume":"4","author":"s","year":"1993","journal-title":"Nanotechnology"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.98"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/29.32286"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1987.1165275"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.1991.238893"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2504774"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1186\/1471-2105-12-221"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2008.4802475"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2012.6463779"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.53"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2148183"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1987.1165274"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CNNA.2012.6331413"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2010.5510929"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2093145.2093146"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/29.32287"},{"key":"ref47","doi-asserted-by":"crossref","first-page":"1150","DOI":"10.1109\/TNANO.2011.2123915","article-title":"Design of quantum-dot cellular automata circuits using cut-set retiming","volume":"10","author":"liu","year":"2011","journal-title":"IEEE Trans Nanotechnol"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2251422"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2010.2079941"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2011.5941489"},{"key":"ref43","first-page":"15","article-title":"Asynchronous solutions for nano-magnetic logic circuits","volume":"7","author":"vacca","year":"2011","journal-title":"ACM J Emerging Technol Comput Syst"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7118804\/06873247.pdf?arnumber=6873247","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,13]],"date-time":"2022-04-13T22:21:33Z","timestamp":1649888493000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6873247\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7,1]]},"references-count":53,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tc.2014.2346208","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2015,7,1]]}}}