{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,28]],"date-time":"2026-07-28T14:27:20Z","timestamp":1785248840150,"version":"3.55.0"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2015,8,1]],"date-time":"2015-08-01T00:00:00Z","timestamp":1438387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2014-HJ-2507"],"award-info":[{"award-number":["2014-HJ-2507"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2015,8,1]]},"DOI":"10.1109\/tc.2014.2360535","type":"journal-article","created":{"date-parts":[[2014,10,2]],"date-time":"2014-10-02T18:46:30Z","timestamp":1412275590000},"page":"2226-2238","source":"Crossref","is-referenced-by-count":52,"title":["IIPS: Infrastructure IP for Secure SoC Design"],"prefix":"10.1109","volume":"64","author":[{"given":"Xinmu","family":"Wang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yu","family":"Zheng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Abhishek","family":"Basak","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","year":"0"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488830"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2013.2249555"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509668"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2011.5954999"},{"key":"ref36","author":"francisco","year":"2006","journal-title":"The Core Test Wrapper Handbook"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2011.5954992"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2012.2210183"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/952532.952593"},{"key":"ref11","first-page":"219","article-title":"Scan design and secure chip","author":"hely","year":"0","journal-title":"Proc 10th IEEE Int On-Line Testing Symp"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-011-5255-2"},{"key":"ref13","first-page":"1","article-title":"RON: An on-chip ring oscillator network for hardware trojan detection","author":"zhang","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref14","first-page":"51","article-title":"Hardware trojan detection using path delay fingerprint","author":"jin","year":"0","journal-title":"Proc IEEE Symp Hardware-Oriented Security Trust(HOST"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2093547"},{"key":"ref16","year":"0"},{"key":"ref17","year":"0"},{"key":"ref18","article-title":"Guest editor&#x2019;s introduction: What is infrastructure IP?","author":"zorian","year":"0","journal-title":"Proc IEEE Des Test Comput"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2004.1347865"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1023\/A:1016545607915"},{"key":"ref4","first-page":"9","article-title":"Physical unclonable functions for device authentication and secret key generation","author":"suh","year":"0","journal-title":"Proc 44th Annu Conf Des Autom"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700564"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2008.4762384"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862745"},{"key":"ref29","year":"0"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.58"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973110"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.89"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"ref9","first-page":"1137","article-title":"Anti-counterfeiting with hardware intrinsic security","author":"leest","year":"0","journal-title":"Proc Conf Des Autom Test Eur"},{"key":"ref1","author":"mangard","year":"2007","journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003786"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003783"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003798"},{"key":"ref24","year":"0"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271086"},{"key":"ref26","first-page":"744","article-title":"Delay fault testing of core-based systems-on-a-chip","author":"xu","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref25","year":"0"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7151894\/06915693.pdf?arnumber=6915693","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:01:08Z","timestamp":1642003268000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6915693\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8,1]]},"references-count":37,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tc.2014.2360535","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2015,8,1]]}}}