{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,17]],"date-time":"2025-12-17T08:23:26Z","timestamp":1765959806237,"version":"3.37.3"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2016,5,1]],"date-time":"2016-05-01T00:00:00Z","timestamp":1462060800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100007225","name":"Ministry of Science and Technology","doi-asserted-by":"publisher","award":["MOST 103-2221-E-001-012-MY2"],"award-info":[{"award-number":["MOST 103-2221-E-001-012-MY2"]}],"id":[{"id":"10.13039\/100007225","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2016,5,1]]},"DOI":"10.1109\/tc.2015.2451660","type":"journal-article","created":{"date-parts":[[2015,7,7]],"date-time":"2015-07-07T21:32:44Z","timestamp":1436304764000},"page":"1467-1483","source":"Crossref","is-referenced-by-count":15,"title":["Disturbance Relaxation for 3D Flash Memory"],"prefix":"10.1109","volume":"65","author":[{"given":"Yu-Ming","family":"Chang","sequence":"first","affiliation":[]},{"given":"Yuan-Hao","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Tei-Wei","family":"Kuo","sequence":"additional","affiliation":[]},{"given":"Yung-Chun","family":"Li","sequence":"additional","affiliation":[]},{"given":"Hsiang-Pang","family":"Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"ref39"},{"article-title":"Flash memory card with block memory address arrangement","year":"1999","author":"shinohara","key":"ref38"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757458"},{"article-title":"3D flash memory device having different dummy word lines and data storage devices including same","year":"2014","author":"nam","key":"ref32"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2011.5937225"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556199"},{"key":"ref37","first-page":"156","article-title":"Non-volatile memory technologies for beyond 2010","author":"shin","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref36","first-page":"1","article-title":"Inherent issues and challenges of program disturbance of 3D NAND flash cell","author":"shim","year":"0","journal-title":"Proc IEEE Int Memory Workshop"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/SNW.2012.6243320"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"70304","DOI":"10.7567\/JJAP.53.070304","article-title":"New program inhibition scheme for high boosting efficiency in three-dimensional NAND array","volume":"53","author":"y","year":"2014","journal-title":"Japanese J Appl Phys"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242476"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339708"},{"key":"ref11","first-page":"6","article-title":"Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process","author":"chin","year":"0","journal-title":"Proc IEEE Int Electron Dev Meeting"},{"key":"ref12","first-page":"507","article-title":"KAST: K-associative sector translation for NAND flash memory in real-time systems","author":"cho","year":"0","journal-title":"Proc Des Autom and Test Eur Conf and Exhib"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.52.06GE02"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071990"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669118"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508271"},{"key":"ref17","first-page":"10.3.1","article-title":"Ultra high density 3D via RRAM in pure 28 nm CMOS process","author":"hsieh","year":"0","journal-title":"Proc IEEE Int Electron Dev Meeting"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228518"},{"key":"ref19","first-page":"68","article-title":"A highly scalable vertical gate (VG) 3D NAND flash with robust program disturb immunity using a novel PN diode decoding structure","author":"hung","year":"0","journal-title":"Proc VLSI Symp Tecnol"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2006.352599"},{"key":"ref4","first-page":"1","article-title":"Memory architecture of 3d vertical gate (3DVG) NAND flash using plural island-gate SSL decoding method and study of it's program inhibit characteristics","author":"chang","year":"0","journal-title":"Proc 4th IEEE Int Memory Workshop"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/11807964_88"},{"article-title":"Wear leveling of static areas in flash memory","year":"2004","author":"ban","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278533"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2008.08.007"},{"key":"ref5","first-page":"187","article-title":"An adaptive striping architecture for flash memory storage systems of embedded systems","author":"chang","year":"0","journal-title":"Proc IEEE Real-Time and Embedded Technol and Appl Symp"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691152"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.126"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2247606"},{"key":"ref9","first-page":"94","article-title":"Error correction for multi-level NAND flash memory using Reed-Solomon codes","author":"chen","year":"0","journal-title":"Proc IEEE Workshop Signal Process Syst"},{"year":"0","key":"ref1","article-title":"Flash file system"},{"key":"ref20","first-page":"192","article-title":"Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory","author":"jang","year":"0","journal-title":"Proc VLSI Symp Tecnol"},{"key":"ref22","first-page":"186","article-title":"Novel vertical-stacked-array-transistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (solid state drive)","author":"kim","year":"0","journal-title":"Proc VLSI Symp Tecnol"},{"key":"ref21","first-page":"136","article-title":"Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices","author":"katsumata","year":"0","journal-title":"Proc VLSI Symp Tecnol"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2235125"},{"key":"ref24","first-page":"188","article-title":"Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage","author":"kim","year":"0","journal-title":"Proc VLSI Symp Tecnol"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176694"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"366","DOI":"10.1109\/TCE.2002.1010143","article-title":"A space-efficient flash translation layer for compactflash systems","volume":"48","author":"kim","year":"2002","journal-title":"IEEE Trans Consum Electron"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233624"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1453775.1453783"},{"key":"ref43","first-page":"29.7.1","article-title":"Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application","author":"whang","year":"0","journal-title":"Proc IEEE Int Electron Dev Meeting"},{"key":"ref25","first-page":"118","article-title":"Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure","author":"lee","year":"0","journal-title":"Proc VLSI Symp Tecnol"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7447853\/07145418.pdf?arnumber=7145418","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:29Z","timestamp":1633919669000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7145418\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,1]]},"references-count":44,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tc.2015.2451660","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2016,5,1]]}}}