{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,15]],"date-time":"2026-01-15T22:42:57Z","timestamp":1768516977872,"version":"3.49.0"},"reference-count":60,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2016,6,1]],"date-time":"2016-06-01T00:00:00Z","timestamp":1464739200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2016,6,1]]},"DOI":"10.1109\/tc.2015.2455978","type":"journal-article","created":{"date-parts":[[2015,7,13]],"date-time":"2015-07-13T18:48:48Z","timestamp":1436813328000},"page":"1678-1691","source":"Crossref","is-referenced-by-count":27,"title":["A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I\/O Characterization"],"prefix":"10.1109","volume":"65","author":[{"given":"Mojtaba","family":"Tarihi","sequence":"first","affiliation":[]},{"given":"Hossein","family":"Asadi","sequence":"additional","affiliation":[]},{"given":"Alireza","family":"Haghdoost","sequence":"additional","affiliation":[]},{"given":"Mohammad","family":"Arjomand","sequence":"additional","affiliation":[]},{"given":"Hamid","family":"Sarbazi-Azad","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","year":"0"},{"key":"ref38","year":"0"},{"key":"ref33","first-page":"1","article-title":"Hybrid nonvolatile disk cache for energy-efficient and high-performance systems","volume":"18","year":"2013","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.32"},{"key":"ref31","first-page":"45","article-title":"Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design","author":"chen","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1416944.1416949"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636097"},{"key":"ref35","first-page":"4","article-title":"A comparison of file system workloads","author":"roselli","year":"0","journal-title":"Proc Annu Conf USENIX Ann Tech Conf"},{"key":"ref34","article-title":"Unix disk access patterns,” Tech. Rep. HPL-92-152, Hewlett-Packard Laboratories","author":"ruemmler","year":"0"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1145\/2421648.2421656"},{"key":"ref28","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","year":"0","journal-title":"Proc Conf Des Autom Test Eur"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4419064"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref2","author":"obrien","year":"0"},{"key":"ref1","author":"shaman","year":"0"},{"key":"ref20","first-page":"268","article-title":"A 90 nm 4 Mb embedded phase-change memory with 1.2 V 12 ns read access time and 1 MB\/s write throughput","author":"de sandre","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf Digest Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796676"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2012.6330621"},{"key":"ref24","first-page":"19.7.1","article-title":"Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance","author":"lee","year":"0","journal-title":"Proc IEEE Int Electron Devices Meet"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1063\/1.3294625"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1038\/nmat3070"},{"key":"ref25","first-page":"52","article-title":"Bi-layered RRAM with unlimited endurance and extremely uniform switching","author":"kim","year":"0","journal-title":"Proc VLSI Technol Symp"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176789"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2008.4637609"},{"key":"ref59","first-page":"421","article-title":"Scavenger: A new last level cache architecture with global block priority","year":"0","journal-title":"Proc 40th Annu IEEE\/ACM Int Symp Microarchit"},{"key":"ref58","article-title":"Relaxing writes in non-volatile processor cache using frequent value locality","author":"arjomand","year":"0","journal-title":"Design Automation Conference (DAC) Work-in-Progress Session"},{"key":"ref57","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","year":"0","journal-title":"Proc Conf Des Autom Test Eur"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993611"},{"key":"ref55","article-title":"ULTRASPARC T2 supplement to the ULTRASPARC architecture","year":"0"},{"key":"ref54","first-page":"554","article-title":"Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement","year":"0","journal-title":"Proc 45th Annu Des Autom Conf"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1787275.1787282"},{"key":"ref52","first-page":"1351","article-title":"CCF-LRU: A new buffer replacement algorithm for flash memory","volume":"55","year":"2008","journal-title":"IEEE Trans Consum Electron"},{"key":"ref10","first-page":"57","article-title":"Design tradeoffs for SSD performance","author":"agrawal","year":"0","journal-title":"Proc USENIX Annu Techn Conf"},{"key":"ref11","author":"obrien","year":"0"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2007.4362191"},{"key":"ref12","author":"shaman","year":"0"},{"key":"ref13","author":"obrien","year":"2012"},{"key":"ref14","article-title":"An overview of SSD write caching","author":"rollins","year":"2012"},{"key":"ref15","article-title":"Flash & DRAM Si scaling challenges, emerging non-volatile memory technology enablement-implications to enterprise storage and server compute systems","author":"yoon","year":"2013","journal-title":"Flash Memory Summit"},{"key":"ref16","article-title":"August 2012 semicondutor general catalog, memories and storage devices","year":"0"},{"key":"ref17","article-title":"The inconvenient truths of NAND flash memory","author":"cooke","year":"2007","journal-title":"Flash Memory Summit"},{"key":"ref18","article-title":"64 Gb, 128 Gb, 256 Gb, 512 Gb Asynchronous\/Synchronous NAND","year":"2009"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669118"},{"key":"ref4","first-page":"9","article-title":"Disk drive level workload characterization","author":"riska","year":"0","journal-title":"Proc USENIX Annu Tech Conf"},{"key":"ref3","author":"shaman","year":"0"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"ref5","first-page":"271","article-title":"Understanding the robustness of SSDs under power fault","author":"zheng","year":"0","journal-title":"Proc USENIX Conf File Storage Technol"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2010.5496998"},{"key":"ref9","article-title":"The disksim simulation environment version 4.0 reference manual","author":"bucy","year":"2008"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2006.1649669"},{"key":"ref45","article-title":"CACTI 5.1","author":"thoziyoor","year":"2008"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.224"},{"key":"ref47","first-page":"16:1","article-title":"BPLRU: A buffer management scheme for improving random writes in flash storage","author":"kim","year":"0","journal-title":"Proc Usenix Conf File and Storage Technologies (FAST 08)"},{"key":"ref42","doi-asserted-by":"crossref","first-page":"422","DOI":"10.1145\/362686.362692","article-title":"Space\/time trade-offs in hash coding with allowable errors","volume":"13","author":"h","year":"1970","journal-title":"Commun ACM"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/PDIS.1996.568672"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7466398\/07155523.pdf?arnumber=7155523","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:44:55Z","timestamp":1642005895000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7155523\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6,1]]},"references-count":60,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tc.2015.2455978","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2016,6,1]]}}}