{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,7]],"date-time":"2026-05-07T12:16:36Z","timestamp":1778156196673,"version":"3.51.4"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2016,6,1]],"date-time":"2016-06-01T00:00:00Z","timestamp":1464739200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"CATRENE CA505 BENEFIC"},{"name":"OpenES","award":["CA703"],"award-info":[{"award-number":["CA703"]}]},{"DOI":"10.13039\/100015034","name":"RESIST","doi-asserted-by":"crossref","award":["CT217"],"award-info":[{"award-number":["CT217"]}],"id":[{"id":"10.13039\/100015034","id-type":"DOI","asserted-by":"crossref"}]},{"name":"ARTEMIS","award":["621429"],"award-info":[{"award-number":["621429"]}]},{"name":"EMC2"},{"name":"DEWI","award":["621353"],"award-info":[{"award-number":["621353"]}]},{"DOI":"10.13039\/501100003766","name":"Ministry of Education of the Czech Republic","doi-asserted-by":"publisher","award":["CZ.1.07\/2.3.00\/30.0034"],"award-info":[{"award-number":["CZ.1.07\/2.3.00\/30.0034"]}],"id":[{"id":"10.13039\/501100003766","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2016,6,1]]},"DOI":"10.1109\/tc.2015.2458859","type":"journal-article","created":{"date-parts":[[2015,7,28]],"date-time":"2015-07-28T14:37:27Z","timestamp":1438094247000},"page":"1882-1895","source":"Crossref","is-referenced-by-count":14,"title":["Power\/Performance Trade-Offs in Real-Time SDRAM Command Scheduling"],"prefix":"10.1109","volume":"65","author":[{"given":"Sven","family":"Goossens","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karthik","family":"Chandrasekar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benny","family":"Akesson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kees","family":"Goossens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2009.5377664"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382172"},{"key":"ref33","article-title":"DDR4 networking design guide introduction","year":"2014"},{"key":"ref32","article-title":"High-level power estimation and optimization of DRAMs","author":"chandrasekar","year":"2014"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2011.17"},{"key":"ref30","author":"chandrasekar","year":"0"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815972"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1145\/1394608.1382128","article-title":"Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems","volume":"36","author":"mutlu","year":"2008","journal-title":"SIGARCH Comput Archit News"},{"key":"ref35","article-title":"Adaptive page management","author":"dodd","year":"2006"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.075"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090857"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.34"},{"key":"ref11","year":"0"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763146"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.270"},{"key":"ref14","year":"0","journal-title":"P4080 QorIQ Multicore Communication Processor Reference Manual"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2008.36"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref17","author":"akesson","year":"2011","journal-title":"Memory Controllers for Real-Time Embedded Systems"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228538"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039388"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488762"},{"key":"ref4","author":"jacob","year":"2007","journal-title":"Memory Systems Cache DRAM Disk"},{"key":"ref27","year":"0"},{"key":"ref3","year":"0"},{"key":"ref6","year":"0"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2010.35"},{"key":"ref5","year":"0"},{"key":"ref8","year":"0"},{"key":"ref7","year":"0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICEAC.2011.6403622"},{"key":"ref9","year":"0"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/977091.977115"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176609"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763145"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176432"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"64","DOI":"10.1145\/2435227.2435260","article-title":"Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions","volume":"12","author":"paolieri","year":"2013","journal-title":"ACM Trans Embedded Comput Syst"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176554"},{"key":"ref42","year":"0"},{"key":"ref24","first-page":"27","article-title":"ROC: A rank-switching, open-row DRAM controller for time-predictable systems","author":"krishnapillai","year":"0","journal-title":"Proc Euromicro Conf Real-Time Syst"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2014.18"},{"key":"ref23","year":"0","journal-title":"DDR3 SDRAM"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/307338.300998"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2011.33"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237004"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925998"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7466398\/07169527.pdf?arnumber=7169527","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:44:55Z","timestamp":1641987895000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7169527\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6,1]]},"references-count":46,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tc.2015.2458859","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2016,6,1]]}}}