{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,21]],"date-time":"2026-09-21T04:51:53Z","timestamp":1789966313757,"version":"4.0.1"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,3,1]],"date-time":"2016-03-01T00:00:00Z","timestamp":1456790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2016,3,1]]},"DOI":"10.1109\/tc.2015.2462811","type":"journal-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T18:52:14Z","timestamp":1438282334000},"page":"781-790","source":"Crossref","is-referenced-by-count":16,"title":["A Novel Scheme for Tolerating Single Event\/Multiple Bit Upsets (SEU\/MBU) in Non-Volatile Memories"],"prefix":"10.1109","volume":"65","author":[{"given":"Wei","family":"Wei","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kazuteru","family":"Namba","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yong-Bin","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fabrizio","family":"Lombardi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2043271"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.897517"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1109\/TDMR.2011.2167233","article-title":"Analysis\n and design of nanoscale CMOS storage elements for single event hardening with multiple node upset","volume":"12","author":"kim","year":"2012","journal-title":"IEEE Trans Device Mater Rel"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/23.903813"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/23.556880"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2008.12"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591515"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2005.15"},{"key":"ref31","first-page":"1","article-title":"A\n fully-parallel step-by-step BCH decoder over composite field for NOR flash memories","author":"chen","year":"0","journal-title":"Proc IEEE Int Symp VLSI Des Autom Test"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2008.4815742"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860675"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2322511"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2186965"},{"key":"ref32","author":"lin","year":"2004","journal-title":"Error Control Coding"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/23.659045"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378631"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.96"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2012.6378203"},{"key":"ref38","first-page":"31.6.1","article-title":"10×10\ufffdnm2 Hf\/HfOx crossbar resistive RAM\n with excellent performance, reliability and low-energy operation","author":"govoreanu","year":"0","journal-title":"Proc IEEE Int Electron Devices Meeting"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2008.2000892"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488683"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1002\/0471792748"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1063\/1.2828864"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003705"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.219"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2006.884788"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070830"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2003.813129"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2190632"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2010.2042818"},{"key":"ref29","first-page":"69","article-title":"Design and analysis of\n non-volatile memory cells for SEU tolerance","author":"wei","year":"0","journal-title":"Proc 17th IEEE Symp Defect Fault Tolerance VLSI Nanotechnol Syst"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669126"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2329915"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2011.2109965"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/16.848282"},{"key":"ref3","first-page":"145","article-title":"A gate leakage reduction strategy for sub-70\ufffdnm memory circuit","author":"elakkumanan","year":"0","journal-title":"Proc IEEE Dallas\/CAS Workshop"},{"key":"ref6","first-page":"291","article-title":"Novel RRAM programming technology for instant-on and high-security FPGAs","author":"xue","year":"0","journal-title":"Proc IEEE 9th Int Conf ASIC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2765491.2765510"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7401237\/7173038.pdf?arnumber=7173038","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,27]],"date-time":"2023-04-27T22:06:14Z","timestamp":1682633174000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7173038\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3,1]]},"references-count":39,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tc.2015.2462811","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2016,3,1]]}}}