{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:42:33Z","timestamp":1771702953853,"version":"3.50.1"},"reference-count":58,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"US National Science Foundation (NSF) CAREER","doi-asserted-by":"publisher","award":["CCF-1208933"],"award-info":[{"award-number":["CCF-1208933"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2016,4,1]]},"DOI":"10.1109\/tc.2015.2506555","type":"journal-article","created":{"date-parts":[[2015,12,9]],"date-time":"2015-12-09T09:36:20Z","timestamp":1449653780000},"page":"1025-1040","source":"Crossref","is-referenced-by-count":15,"title":["WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory"],"prefix":"10.1109","volume":"65","author":[{"given":"Poovaiah M.","family":"Palangappa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiayin","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kartik","family":"Mohanram","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"2","article-title":"Correcting charge-constrained errors in the rank-modulation scheme","volume":"37","author":"jiang","year":"2010","journal-title":"IEEE Trans Inf Theory"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2009.2018336"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.377981"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref30","article-title":"SPEC CPU2006","year":"2006"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"217","DOI":"10.1145\/1508284.1508270","article-title":"Gordon: Using flash memory to build fast, power-efficient clusters for data-intensive applications","volume":"44","author":"m","year":"2009","journal-title":"ACM SIGPLAN Notices"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(82)90344-8"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref34","article-title":"Cacti 6.0: A tool to understand large caches","year":"2009"},{"key":"ref28","first-page":"1","article-title":"Write-once-memory-code phase change memory","author":"li","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2052640"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref2","article-title":"Exascale computing study: Technology challenges in achieving exascale systems","author":"kogge","year":"2008"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1201\/b11354"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024738"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081394"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024939"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228374"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722186"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"5102","DOI":"10.1109\/TIT.2013.2257916","article-title":"Time-space constrained codes for phase-change memories","volume":"59","author":"qin","year":"2013","journal-title":"IEEE Trans Inf Theory"},{"key":"ref25","first-page":"1","article-title":"Constrained codes for phase-change memories","author":"jiang","year":"0","journal-title":"Proc IEEE Inf Theory Workshop"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.62"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333717"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555759"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2011.6008569"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1002\/0471684228.egp09575"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228519"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995911"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993611"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1116\/1.2752515"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337203"},{"key":"ref40","first-page":"217","article-title":"WoM-SET: Lowering write power of proactive-SET based PCM write strategy using WoM code","author":"zhang","year":"0","journal-title":"Proc Int Symp Low Power Electron Des"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228520"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2165974"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2012.39"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"ref17","first-page":"282","article-title":"Accelerating write by exploiting PCM asymmetries","author":"yue","year":"0","journal-title":"Proc IEEE 19th Int Symp High-Perform Comput Archit"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.202"},{"key":"ref3","article-title":"International Technology Roadmap for Semiconductors","year":"2011"},{"key":"ref6","first-page":"46","article-title":"A 20nm 1.8V 8GB PRAM with 40MB\/s program bandwidth","author":"song","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Techn Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.888349"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1063\/1.2963196"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"ref49","first-page":"51","article-title":"Compression architecture for bit-write reduction in non-volatile memory technologies","author":"dgien","year":"0","journal-title":"Proc IEEE\/ACM Int Symp Nanoscale Archit"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2007.378936"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020989"},{"key":"ref45","first-page":"1","article-title":"A limit study on the potential of compression for improving memory system performance, power consumption, and cost","volume":"7","author":"mahapatra","year":"2005","journal-title":"J Instruction-Level Parallelism"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147086"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.6"},{"key":"ref42","first-page":"14","article-title":"Enhancing lifetime and security of phase change memories via start-gap wear leveling","author":"qureshi","year":"0","journal-title":"Proc 42nd Annu IEEE\/ACM Int Symp Microarchit"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.27"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816014"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2012.90"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/12\/7430016\/7349141-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7430016\/07349141.pdf?arnumber=7349141","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:56:18Z","timestamp":1649444178000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7349141\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4,1]]},"references-count":58,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tc.2015.2506555","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2016,4,1]]}}}