{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T16:22:48Z","timestamp":1774369368571,"version":"3.50.1"},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100006129","name":"National Funds through FCT\/MEC","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006129","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Portuguese Foundation for Science and Technology"},{"DOI":"10.13039\/501100008530","name":"ERDF","doi-asserted-by":"crossref","award":["PT2020"],"award-info":[{"award-number":["PT2020"]}],"id":[{"id":"10.13039\/501100008530","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100008530","name":"ERDF","doi-asserted-by":"crossref","award":["UID\/CEC\/04234\/2013"],"award-info":[{"award-number":["UID\/CEC\/04234\/2013"]}],"id":[{"id":"10.13039\/501100008530","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100006129","name":"FCT\/MEC","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006129","id-type":"DOI","asserted-by":"publisher"}]},{"name":"EU ARTEMIS JU within projec","award":["ARTEMIS\/0001\/2013"],"award-info":[{"award-number":["ARTEMIS\/0001\/2013"]}]},{"name":"EU ARTEMIS JU within projec","award":["621429 (EMC2)"],"award-info":[{"award-number":["621429 (EMC2)"]}]},{"name":"EU ARTEMIS JU within projec","award":["621353 (DEWI)"],"award-info":[{"award-number":["621353 (DEWI)"]}]},{"name":"EU FP7","award":["288008"],"award-info":[{"award-number":["288008"]}]},{"name":"T-CREST","award":["318763"],"award-info":[{"award-number":["318763"]}]},{"name":"T-CREST","award":["288248"],"award-info":[{"award-number":["288248"]}]},{"name":"T-CREST","award":["CA505"],"award-info":[{"award-number":["CA505"]}]},{"name":"T-CREST","award":["CA703"],"award-info":[{"award-number":["CA703"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2017,2,1]]},"DOI":"10.1109\/tc.2016.2595581","type":"journal-article","created":{"date-parts":[[2016,7,27]],"date-time":"2016-07-27T18:47:57Z","timestamp":1469645277000},"page":"212-225","source":"Crossref","is-referenced-by-count":16,"title":["A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems"],"prefix":"10.1109","volume":"66","author":[{"given":"Manil Dev","family":"Gomony","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jamie","family":"Garside","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2949-2080","authenticated-orcid":false,"given":"Benny","family":"Akesson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Neil","family":"Audsley","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kees","family":"Goossens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2015.7108439"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1629335.1629372"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/j.scico.2015.06.006"},{"key":"ref32","author":"sriram","year":"2009","journal-title":"Embedded Multiprocessors Scheduling and Synchronization"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/18.61109"},{"key":"ref30","first-page":"200","article-title":"Performance analysis of SOC architectures based on latency-rate servers","author":"vink","year":"0","journal-title":"Proc Des Autom Test Europe"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.148"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.075"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1269843.1269846"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2015.04.001"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008052406396"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/90.731196"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.58"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090857"},{"key":"ref1","year":"2013"},{"key":"ref20","first-page":"53","article-title":"A time-predictable memory network-on-chip","author":"schoeberl","year":"0","journal-title":"Proc Int Workshop Worst-Case Execution Time Anal"},{"key":"ref22","article-title":"Interconnect and memory organization in SOCs for advanced set-top boxes and TV &#x2014; Evolution, analysis, and trends","author":"goossens","year":"2004","journal-title":"Interconnect-Centric Design for Advanced SoC and NoC"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763085"},{"key":"ref24","first-page":"1","article-title":"Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems","author":"gomony","year":"0","journal-title":"Proc Des Autom Test Europe Conf Exhibition"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492735"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0390"},{"key":"ref25","first-page":"317","article-title":"Dynamic control for mixed-critical networks-on-chip","author":"kostrzewa","year":"0","journal-title":"Proc Real-Time Syst Symp"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6658989"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2015.12"},{"key":"ref11","first-page":"317","article-title":"A predictable and command-level priority-based DRAM controller for mixed-criticality systems","author":"kim","year":"0","journal-title":"Proc IEEE Real-Time Embedded Technol Appl Symp"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1016\/j.jss.2015.11.019"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2014.6910550"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/581199.581253"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.26"},{"key":"ref15","article-title":"Arbiters: Design ideas and coding styles","author":"weber","year":"0","journal-title":"Proc Synopsys Users Group"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2008.21"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSoC.2013.6675268"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2012.54"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289855"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763146"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090858"},{"key":"ref6","article-title":"Composability and predictability for independent application development, verification, and execution","author":"akesson","year":"2010","journal-title":"Multiprocessor System-on-ChipHardware Design and Tool Integration"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2008.36"},{"key":"ref8","author":"akesson","year":"2011","journal-title":"Memory Controllers for Real-Time Embedded Systems"},{"key":"ref7","year":"2015"},{"key":"ref49","author":"garside","year":"2016"},{"key":"ref9","article-title":"Mixed criticality systems&#x2014;a review","author":"burns","year":"2013"},{"key":"ref46","article-title":"MICRON DDR3 SDRAM Specification","year":"2006"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2458859"},{"key":"ref48","article-title":"Multi-core processors","year":"2014"},{"key":"ref47","article-title":"Software considerations in airborne systems and equipment certification","year":"2012"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763145"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2009.13"},{"key":"ref44","doi-asserted-by":"crossref","first-page":"64:1","DOI":"10.1145\/2435227.2435260","article-title":"Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions","volume":"12","author":"paolieri","year":"2013","journal-title":"ACM Trans Embedded Comput Syst"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-015-9235-y"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/7815462\/07523935.pdf?arnumber=7523935","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:12:32Z","timestamp":1642003952000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7523935\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2,1]]},"references-count":50,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tc.2016.2595581","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,2,1]]}}}