{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,28]],"date-time":"2026-02-28T23:50:15Z","timestamp":1772322615654,"version":"3.50.1"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"US National Science Foundation","doi-asserted-by":"publisher","award":["1311706"],"award-info":[{"award-number":["1311706"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"US National Science Foundation","doi-asserted-by":"publisher","award":["1337198"],"award-info":[{"award-number":["1337198"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"US National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2017,9,1]]},"DOI":"10.1109\/tc.2017.2690855","type":"journal-article","created":{"date-parts":[[2017,4,4]],"date-time":"2017-04-04T22:41:38Z","timestamp":1491345698000},"page":"1478-1490","source":"Crossref","is-referenced-by-count":16,"title":["An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory"],"prefix":"10.1109","volume":"66","author":[{"given":"Mengjie","family":"Mao","sequence":"first","affiliation":[]},{"given":"Wujie","family":"Wen","sequence":"additional","affiliation":[]},{"given":"Yaojun","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Yiran","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Hai","family":"Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2013.6629258"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485952"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522330"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540716"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2019608.2019612"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155675"},{"key":"ref37","first-page":"247","article-title":"SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading","author":"yu","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.18"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815998"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485934"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540718"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540719"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1063\/1.2830964"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref1","article-title":"The geforece gtx 680","year":"2012"},{"key":"ref20","article-title":"Operand collector architecture","author":"liu","year":"2010","journal-title":"U S Patent 7 834 881"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333707"},{"key":"ref21","article-title":"CUDA","year":"0"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155656"},{"key":"ref23","article-title":"Nvidia kepler architecture","year":"2012"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451158"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"ref10","first-page":"22","article-title":"CACTI 6.0: A tool to model large caches","author":"muralimanohar","year":"2009","journal-title":"HP Laboratories"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.365"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522331"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488799"},{"key":"ref13","article-title":"Nvidia fermi architecture","year":"2009"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"ref15","first-page":"230","article-title":"Low-current perpendicular domain wall motion cell for scalable high-speed MRAM","author":"fukami","year":"2009","journal-title":"Proc Symp VLSI Technol"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2013.6629268"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"190","DOI":"10.1126\/science.1145799","article-title":"Magnetic domain-wall racetrack memory","volume":"320","author":"parkin","year":"2008","journal-title":"Science"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000093"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485964"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref7","article-title":"Parboil: A revised benchmark suite for scientific and commercial throughput computing","author":"stratton","year":"2012"},{"key":"ref49","article-title":"Performance-centric register file design for GPUs using racetrack memory","author":"wang","year":"2016","journal-title":"the Proc of Asia South Pacific Design Automation (ASP-DAC)"},{"key":"ref9","article-title":"CUDA SDK","year":"0"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131603"},{"key":"ref45","doi-asserted-by":"crossref","first-page":"1688","DOI":"10.1126\/science.1108813","article-title":"Magnetic domain-wall logic","volume":"309","author":"allwood","year":"2005","journal-title":"Science"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665710"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131604"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522337"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"ref44","article-title":"Shiftable magnetic shift register and method of using the same","author":"parkin","year":"2004","journal-title":"U S Patent 6 834 005"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1063\/1.333530"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/12\/8003558\/7891951-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8003558\/07891951.pdf?arnumber=7891951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:56:18Z","timestamp":1649444178000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7891951\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9,1]]},"references-count":49,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tc.2017.2690855","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2017,9,1]]}}}