{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T09:58:32Z","timestamp":1740131912964,"version":"3.37.3"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2018,1,1]]},"DOI":"10.1109\/tc.2017.2723878","type":"journal-article","created":{"date-parts":[[2017,7,6]],"date-time":"2017-07-06T18:09:23Z","timestamp":1499364563000},"page":"9-15","source":"Crossref","is-referenced-by-count":11,"title":["Analytical Miss Rate Calculation of L2 Cache from the RD Profile of L1 Cache"],"prefix":"10.1109","volume":"67","author":[{"given":"Jasmine Madonna","family":"Sabarimuthu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0676-512X","authenticated-orcid":false,"given":"T. G.","family":"Venkatesh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854347"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1140103.1140304"},{"key":"ref12","first-page":"76","article-title":"Cache contention and application performance prediction\n for multi-core systems","author":"xu","year":"2010","journal-title":"Proc IEEE Int Symp Perform Anal Syst Softw"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2013.01.010"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2009.31"},{"article-title":"An analytical model of locality and caching","year":"1999","author":"brehob","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2003.09.004"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446067"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/12.543711"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2512873"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/225830.223990"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"article-title":"Benchmarking modern multiprocessors","year":"2011","author":"bienia","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782836"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2015.7095785"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452069"},{"key":"ref8","first-page":"350","article-title":"Reuse distance as a metric for cache behavior","author":"beyls","year":"2001","journal-title":"Proc IASTED Conf Parallel Distrib Comput Syst"},{"article-title":"Optimizing a cache back invalidation policy","year":"2013","author":"balakrishnan","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2465529.2465756"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2004.1291352"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000109"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/12.40842"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1629335.1629370"},{"key":"ref24","first-page":"1","article-title":"On the nature of cache miss behavior: Is it\n $\\sqrt{2}$","volume":"10","author":"hartstein","year":"2008","journal-title":"J Instruction-Level Parallelism"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.5009230"},{"key":"ref26","article-title":"Sniper:\n Exploring the level of abstraction for scalable and accurate parallel multi-core simulation","author":"carlson","year":"2011","journal-title":"Proc Int Conf High Perform Comput Netw Storage Anal"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/200912.200918"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8176066\/07970187.pdf?arnumber=7970187","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:23:36Z","timestamp":1642004616000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7970187\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1,1]]},"references-count":29,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tc.2017.2723878","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2018,1,1]]}}}