{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,8]],"date-time":"2026-02-08T07:56:40Z","timestamp":1770537400881,"version":"3.49.0"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2018,2,1]],"date-time":"2018-02-01T00:00:00Z","timestamp":1517443200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Secretaria de Estado de Investigacion Desarrollo e Innovacion","award":["ESP2014-54505-C2-1-R"],"award-info":[{"award-number":["ESP2014-54505-C2-1-R"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2018,2,1]]},"DOI":"10.1109\/tc.2017.2737996","type":"journal-article","created":{"date-parts":[[2017,8,11]],"date-time":"2017-08-11T18:28:02Z","timestamp":1502476082000},"page":"299-304","source":"Crossref","is-referenced-by-count":22,"title":["Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2424-8679","authenticated-orcid":false,"given":"Alexis","family":"Ramos","sequence":"first","affiliation":[]},{"given":"Anees","family":"Ullah","sequence":"additional","affiliation":[]},{"given":"Pedro","family":"Reviriego","sequence":"additional","affiliation":[]},{"given":"Juan Antonio","family":"Maestro","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2006.382112"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176811"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.181"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.68"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1086228.1086266"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2016.06.019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/RADECS.2008.5782755"},{"key":"ref18","article-title":"Hardware and software fault-tolerance of softcore processors\n implemented in SRAM-based FPGAs","author":"rollins","year":"2012"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339177"},{"key":"ref4","article-title":"The RISC-V Instruction Set Manual","author":"waterman","year":"2017"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.61"},{"key":"ref6","article-title":"7\n series FPGAs memory resources (ver 1.12)","year":"2016"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1416944.1416947"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2226585"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2000850"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2246581"},{"key":"ref9","article-title":"lowRISC trace debugger project","year":"2016"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2629556"},{"key":"ref20","first-page":"23","article-title":"7 series FPGAs configurable logic block (ver 1.8)","year":"2016"},{"key":"ref22","article-title":"lowRISC Configuration Parameters","year":"0"},{"key":"ref21","article-title":"Artix-7 FPGAs data sheet: DC and AC switching characteristics","year":"2016"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2498313"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927478"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2017.06.032"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8255532\/08008792.pdf?arnumber=8008792","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:24:25Z","timestamp":1642004665000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8008792\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,1]]},"references-count":25,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tc.2017.2737996","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2018,2,1]]}}}