{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T16:33:33Z","timestamp":1774802013786,"version":"3.50.1"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003130","name":"Fonds Wetenschappelijk Onderzoek","doi-asserted-by":"publisher","award":["G.0144.17N"],"award-info":[{"award-number":["G.0144.17N"]}],"id":[{"id":"10.13039\/501100003130","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003130","name":"Fonds Wetenschappelijk Onderzoek","doi-asserted-by":"publisher","award":["G.0434.16N"],"award-info":[{"award-number":["G.0434.16N"]}],"id":[{"id":"10.13039\/501100003130","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ERC AdG","award":["741097"],"award-info":[{"award-number":["741097"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2018,6,1]]},"DOI":"10.1109\/tc.2017.2779480","type":"journal-article","created":{"date-parts":[[2017,12,4]],"date-time":"2017-12-04T19:20:03Z","timestamp":1512415203000},"page":"830-846","source":"Crossref","is-referenced-by-count":14,"title":["Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8291-4230","authenticated-orcid":false,"given":"Ajeya","family":"Naithani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2587-7541","authenticated-orcid":false,"given":"Stijn","family":"Eyerman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8792-4473","authenticated-orcid":false,"given":"Lieven","family":"Eeckhout","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"1","article-title":"R2cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores","author":"kriebel","year":"2015","journal-title":"Proc Int Conf Hardw \/Softw Codes Syst Synthesis"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2961059"},{"key":"ref33","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01723-0","author":"sorin","year":"2009","journal-title":"Fault Tolerant Computer Architecture"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2509136.2509529"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.33"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430581"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2004.1276550"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416629"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485966"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151001"},{"key":"ref29","first-page":"177","article-title":"Fairness-aware scheduling on single-ISA heterogeneous multi-cores","author":"van craeynest","year":"2013","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.12"},{"key":"ref20","first-page":"153","article-title":"Area, delay and power comparison of adder topologies","volume":"3","author":"uma","year":"2012","journal-title":"International Journal of VLSI and Communication Systems"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237024"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.56"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555792"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310764"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926955"},{"key":"ref12","article-title":"Big.LITTLE processing with ARM Cortex-A15 & Cortex-A7: Improving energy efficiency in high-performance mobile platforms","author":"greenhalgh","year":"2011"},{"key":"ref13","article-title":"Variable SMP – a multi-core CPU architecture for low power and high performance","year":"2011"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169046"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237019"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.37"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541974"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056028"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253181"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/23.556880"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.18"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250725"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.855790"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2532862"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310780"},{"key":"ref46","doi-asserted-by":"crossref","first-page":"927","DOI":"10.1145\/1629911.1630149","article-title":"efficient program scheduling for heterogeneous multi-core processors","author":"jian chen","year":"2009","journal-title":"2009 46th ACM\/IEEE Design Automation Conference dac"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.34"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/1531793.1531804"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755928"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816023"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.9"},{"key":"ref44","first-page":"129","article-title":"Versatile prediction and fast estimation of architectural vulnerability factor from processor performance metrics","author":"lide","year":"2009","journal-title":"Proc Int Symp High-Perform Comput Arch"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250726"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8356015\/08126846.pdf?arnumber=8126846","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,9]],"date-time":"2022-08-09T22:01:49Z","timestamp":1660082509000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8126846\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6,1]]},"references-count":49,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tc.2017.2779480","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,6,1]]}}}