{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T08:48:10Z","timestamp":1774687690785,"version":"3.50.1"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Dutch Ministry of Economische Zaken"},{"name":"Province of Drenthe"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2018,6,1]]},"DOI":"10.1109\/tc.2017.2780239","type":"journal-article","created":{"date-parts":[[2017,12,6]],"date-time":"2017-12-06T19:17:38Z","timestamp":1512587858000},"page":"755-770","source":"Crossref","is-referenced-by-count":31,"title":["Analytic Multi-Core Processor Model for Fast Design-Space Exploration"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7191-4120","authenticated-orcid":false,"given":"Rik","family":"Jongerius","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6842-9036","authenticated-orcid":false,"given":"Andreea","family":"Anghel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9112-146X","authenticated-orcid":false,"given":"Gero","family":"Dittmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovanni","family":"Mariani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0639-412X","authenticated-orcid":false,"given":"Erik","family":"Vermij","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4506-5732","authenticated-orcid":false,"given":"Henk","family":"Corporaal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","article-title":"Auto-vectorization in LLVM.","year":"0"},{"key":"ref38","year":"0"},{"key":"ref33","article-title":"CACTI 5.1","author":"thoziyoor","year":"2008"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78153-0_21"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2006.1620789"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261391"},{"key":"ref36","article-title":"Graph 500 benchmark.","year":"0"},{"key":"ref35","article-title":"SPEC CPU2006 benchmark description.","year":"0"},{"key":"ref34","article-title":"International technology roadmap for semiconductors","year":"2012"},{"key":"ref10","first-page":"195","article-title":"Efficiently\n exploring architectural design spaces via predictive modeling","author":"\u00efpek","year":"2006","journal-title":"Proc Int Conf Arch Support Program Lang Operat Syst"},{"key":"ref40","article-title":"Instruction tables","author":"fog","year":"2016"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028681"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815967"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2177457"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2379634"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2602458.2602462"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1534909.1534910"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250712"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70817"},{"key":"ref19","first-page":"32","article-title":"Micro-architecture independent analytical\n processor performance and power modeling","author":"van den steen","year":"2015","journal-title":"Proc IEEE Int Symp Perform Anal Syst Softw"},{"key":"ref28","article-title":"Cortex-A15 processor - ARM.","year":"2016"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref27","article-title":"Intel Xeon processor E5–2697 v3 (35M cache, 2.60 GHz)\n specifications.","year":"2016"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357136"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485963"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1005686.1005691"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref8","first-page":"382","article-title":"Accurate source-level simulation of embedded software with respect to compiler optimizations","author":"wang","year":"2012","journal-title":"Proc Conf Des Autom Test Eur"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2578882"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844457"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168881"},{"key":"ref1","first-page":"52:1","article-title":"Sniper:\n Exploring the level of abstraction for scalable and accurate parallel multi-core simulation","author":"carlson","year":"2011","journal-title":"Proc Int Conf High Perform Comput Netw Storage Anal"},{"key":"ref46","article-title":"Exascale computer system design: The Square Kilometre Array","author":"jongerius","year":"2016"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2547387"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/JSTSP.2008.2005290"},{"key":"ref22","first-page":"76","article-title":"Cache contention and application performance prediction\n for multi-core systems","author":"xu","year":"2010","journal-title":"Proc IEEE Int Symp Perform Anal Syst Softw"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-016-0412-y"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798270"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/996841.996853"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835955"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-22047-5_21"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1944862.1944885"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2014.235"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ICPPW.2010.38"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-016-0410-0"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8356015\/08168422.pdf?arnumber=8168422","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:22:18Z","timestamp":1642004538000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8168422\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6,1]]},"references-count":47,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tc.2017.2780239","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2018,6,1]]}}}