{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T19:54:40Z","timestamp":1723060480398},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2018]]},"DOI":"10.1109\/tc.2018.2796077","type":"journal-article","created":{"date-parts":[[2018,1,19]],"date-time":"2018-01-19T19:21:01Z","timestamp":1516389661000},"page":"1-1","source":"Crossref","is-referenced-by-count":10,"title":["Exploring the Design Space of Fair Scheduling Supports for Asymmetric Multicore Systems"],"prefix":"10.1109","author":[{"given":"Changdae","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaehyuk","family":"Huh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755928"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000071"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237019"},{"key":"ref13","first-page":"177","article-title":"Fairness-aware scheduling on single-ISA heterogeneous multi-cores","author":"van craeynest","year":"2013","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/238721.238766"},{"key":"ref15","article-title":"Surplus fair scheduling: A\n proportional-share CPU scheduling algorithm for symmetric multiprocessors","author":"chandra","year":"2000","journal-title":"Proc Symp Oper Syst Des Implementation"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.70755"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310764"},{"key":"ref18","article-title":"Fairness-oriented OS scheduling support for multicore systems","author":"kim","year":"2016","journal-title":"Proc Int Conf Supercomput"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1787275.1787281"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.40"},{"key":"ref3","article-title":"Big.LITTLE processing with ARM Cortex-A15 & Cortex-A7","author":"greenhalgh","year":"2011","journal-title":"ARM Whitepaper"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1145\/1531793.1531804","article-title":"HASS: A scheduler for heterogeneous multicore\n systems","volume":"43","author":"shelepov","year":"2009","journal-title":"ACM SIGOPS Operating Syst Rev"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798265"},{"key":"ref8","first-page":"1","article-title":"Operating system support for overlapping-ISA heterogeneous multi-core architectures","author":"li","year":"2010","journal-title":"Proc IEEE Int Symp High Perform Comput Archit"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362694"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000067"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755929"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654085"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151001"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508274"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000107"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485936"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/4358213\/08265024.pdf?arnumber=8265024","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T13:22:40Z","timestamp":1643203360000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8265024\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/tc.2018.2796077","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2018]]}}}