{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T09:58:43Z","timestamp":1740131923456,"version":"3.37.3"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2018,12,1]],"date-time":"2018-12-01T00:00:00Z","timestamp":1543622400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"HeGaoJi Program of China","award":["2014ZX01020-301-001"],"award-info":[{"award-number":["2014ZX01020-301-001"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2018,12,1]]},"DOI":"10.1109\/tc.2018.2844351","type":"journal-article","created":{"date-parts":[[2018,6,8]],"date-time":"2018-06-08T18:53:00Z","timestamp":1528483980000},"page":"1780-1793","source":"Crossref","is-referenced-by-count":3,"title":["Reconfigurable Instruction-Based Multicore Parallel Convolution and Its Application in Real-Time Template Matching"],"prefix":"10.1109","volume":"67","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3555-5092","authenticated-orcid":false,"given":"Quan","family":"Zhou","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xin","family":"Yan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref38","article-title":"Performance comparison of GPU, DSP and FPGA implementations of image processing and computer vision algorithms in embedded systems","author":"fykse","year":"2013","journal-title":"Master's thesis"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1109\/76.981846","article-title":"On the data reuse and memory bandwidth analysisfor full-search block-matching VLSI architecture","volume":"12","author":"tuan","year":"0","journal-title":"IEEE Trans Circuits Syst Video Technol"},{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/NOCS.2014.7008757"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/TC.2011.100"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/TVLSI.2015.2405614"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1007\/s11390-017-1765-4"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1109\/TUFFC.2010.1554"},{"key":"ref35","first-page":"1","article-title":"Speed-up template matching through integral image based weak classifiers","volume":"1","author":"wu","year":"2014","journal-title":"J Pattern Recognit Res"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1109\/ULTSYM.2010.5935539"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.2991\/mcei-16.2016.137"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1145\/2644865.2541967","article-title":"DianNao: Asmall-footprint high-throughput accelerator for ubiquitous machine-learning","volume":"49","author":"chen","year":"2014","journal-title":"ACM SIGPLAN Notices"},{"year":"2014","author":"krizhevsky","article-title":"One weird trick for parallelizing convolutional neural networks","key":"ref12"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/IGARSS.2006.255"},{"key":"ref14","first-page":"52","article-title":"On the use of small 2D convolutions on GPUs","year":"0","journal-title":"Proc Int Symp Comput Archit"},{"key":"ref15","first-page":"120","article-title":"Fast template matching","volume":"32","author":"lewis","year":"0","journal-title":"Vis Interface"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/TPAMI.1984.4767532"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/TVLSI.2007.902210"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1007\/s11554-007-0066-5"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/CANDAR.2013.61"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/MC.1982.1653825"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1117\/12.2002096"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1002\/cpe.3752"},{"key":"ref3","article-title":"ESA's roadmap for next generation payload data processors","volume":"1","author":"trautner","year":"0","journal-title":"Proc Data Syst Aerosp"},{"key":"ref6","article-title":"Revealer1601 - A multiple-core digital signal processor for demanding space applications","author":"cao","year":"0","journal-title":"the 66th International Astronautical Congress"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1145\/2593069.2593126"},{"key":"ref5","article-title":"A reliable multicore processor design for space applications","author":"cao","year":"0","journal-title":"Proceedings of the 65th International Astronautical Congress"},{"key":"ref8","first-page":"1248","article-title":"Fast implementation of cross correlation tracking algorithm using multi-core DSP","volume":"23","author":"tian","year":"2013","journal-title":"High Technol Lett"},{"key":"ref7","article-title":"A radiation hardened multicore DSP processor designed for space missions","author":"cao","year":"0","journal-title":"the 66th International Astronautical Congress"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ESTEL.2012.6400064"},{"key":"ref9","first-page":"20","article-title":"Application of 2D convolution in digital image processing","volume":"6","author":"siddiqui","year":"2016","journal-title":"ASIAN J Eng Sci Technol"},{"key":"ref1","article-title":"Ongoing developments of future payload data processing platforms at ESA","author":"trautner","year":"0","journal-title":"ESA\/CNES Conf On-Board Payload Data Compression"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1002\/9780470828519"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1016\/j.sysarc.2012.06.002"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1016\/j.micpro.2004.10.004"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1145\/2701126.2701213"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1109\/ICSMC.2009.5346737"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/ICIP.2013.6738436"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/HPCC-CSS-ICESS.2015.94"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8525378\/08375740.pdf?arnumber=8375740","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:10:22Z","timestamp":1642003822000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8375740\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12,1]]},"references-count":38,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tc.2018.2844351","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2018,12,1]]}}}