{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,25]],"date-time":"2026-01-25T18:23:12Z","timestamp":1769365392764,"version":"3.49.0"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2019,3,1]]},"DOI":"10.1109\/tc.2018.2871096","type":"journal-article","created":{"date-parts":[[2018,9,20]],"date-time":"2018-09-20T22:07:30Z","timestamp":1537481250000},"page":"314-330","source":"Crossref","is-referenced-by-count":18,"title":["Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1706-5164","authenticated-orcid":false,"given":"Sunil","family":"Dutt","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8406-2043","authenticated-orcid":false,"given":"Satyabrata","family":"Dash","sequence":"additional","affiliation":[]},{"given":"Sukumar","family":"Nandi","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2189-3656","authenticated-orcid":false,"given":"Gaurav","family":"Trivedi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2605382"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429542"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926993"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/RADIOELEK.2016.7477392"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3094124"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2803081"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2317180"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001399"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.146"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897981"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2751163"},{"key":"ref40","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2906199"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2016.101"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.75"},{"key":"ref14","author":"parhami","year":"2010","journal-title":"Computer Arithmetic Algorithms and Hardware Designs"},{"key":"ref15","first-page":"69","article-title":"An enhanced low-power high-speed adder for error-tolerant application","author":"zhu","year":"2009","journal-title":"Proc 12th Intl Symp on Integrated Circuits"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403679"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2027626"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2013.6720793"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744778"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2465787.2465794"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691096"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2465787.2465789"},{"key":"ref6","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062306"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-27392-1"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488873"},{"key":"ref7","article-title":"Advancing computer systems without technology progress","author":"hill","year":"2012","journal-title":"Proc ISAT outbrief DARPA\/ISAT Workshop"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2893356"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569370"},{"key":"ref1","author":"weste","year":"2010","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref20","first-page":"1","article-title":"Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI","author":"soares","year":"2015","journal-title":"Proc IEEE Int New Circuits Syst Conf"},{"key":"ref45","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1007\/978-3-540-73554-0_16","article-title":"Using river formation dynamics to design heuristic algorithms","author":"rabanal","year":"2007","journal-title":"Proc 6th Int Conf Unconventional Comput"},{"key":"ref22","first-page":"67","article-title":"Speeding up processing with approximation circuits","volume":"37","author":"lu","year":"2004","journal-title":"IEEE Trans Comput"},{"key":"ref21","first-page":"40:1","article-title":"Analysis and design of adders for approximate computing","volume":"17","author":"dutt","year":"2017","journal-title":"ACM Trans Embed Comput Syst"},{"key":"ref42","year":"0"},{"key":"ref24","first-page":"1449","article-title":"A new approximate adder with low relative error and correct sign calculation","author":"hu","year":"2015","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2564699"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763154"},{"key":"ref44","first-page":"116","article-title":"A brief review of nature-inspired algorithms for optimization","volume":"80","author":"fister jr","year":"2013","journal-title":"Elektrotehniski Vestnik"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691108"},{"key":"ref43","author":"sutherland","year":"1999","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228509"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8637885\/08468108.pdf?arnumber=8468108","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:06:48Z","timestamp":1657746408000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8468108\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3,1]]},"references-count":45,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tc.2018.2871096","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,3,1]]}}}