{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,14]],"date-time":"2025-11-14T07:33:48Z","timestamp":1763105628909,"version":"3.37.3"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"US National Science Foundation","award":["CCF-1618039"],"award-info":[{"award-number":["CCF-1618039"]}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2019,5,1]]},"DOI":"10.1109\/tc.2018.2886884","type":"journal-article","created":{"date-parts":[[2018,12,14]],"date-time":"2018-12-14T22:19:29Z","timestamp":1544825969000},"page":"646-659","source":"Crossref","is-referenced-by-count":13,"title":["Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2894-6503","authenticated-orcid":false,"given":"Hsing-Min","family":"Chen","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6676-3121","authenticated-orcid":false,"given":"Shin-Ying","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Trevor","family":"Mudge","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9032-7239","authenticated-orcid":false,"given":"Carole-Jean","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Chaitali","family":"Chakrabarti","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref39","DOI":"10.1145\/1454115.1454152"},{"year":"2011","article-title":"CUDA C\/C++ SDK code samples v4.0","key":"ref38"},{"year":"0","author":"koopman","article-title":"Best CRC polynomials","key":"ref33"},{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/JRPROC.1961.287814"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/TCOM.1984.1096175"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1145\/2503210.2503243"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1145\/2485922.2485958"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1145\/272991.272995"},{"doi-asserted-by":"publisher","key":"ref35","DOI":"10.1109\/ACSSC.2003.1292358"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1109\/DSN.2004.1311885"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/MM.2010.103"},{"year":"2014","article-title":"NVIDIA GeForce GTX 750 Ti: Featuring first-generation Maxwell GPU technology, designed for extreme performance per watt","key":"ref27"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"285","DOI":"10.1145\/2366231.2337192","article-title":"LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems","author":"udipi","year":"2012","journal-title":"Proc Int Symp Comput Archit"},{"year":"2016","journal-title":"WP-08019&#x2013;001 v01 1","article-title":"Nvidia Tesla P100 - Whitepaper","key":"ref2"},{"year":"2015","journal-title":"High-bandwidth Memory (HBM) DRAM","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/HPCA.2015.7056025"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/TCSII.2013.2291091"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/HPCA.2016.7446094"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/ISCA.2012.6237047"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1145\/2830772.2830799"},{"year":"2015","article-title":"The compute architecture of Intel processor graphics Gen9","key":"ref26"},{"year":"2009","article-title":"NVIDIA&#x2019;s next generation CUDA compute architecture: Fermi","key":"ref25"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1145\/2304576.2304582"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1145\/2957758"},{"doi-asserted-by":"publisher","key":"ref40","DOI":"10.1109\/IISWC.2013.6704684"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/TEST.2014.7035318"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/MICRO.2014.57"},{"year":"2013","journal-title":"High-bandwidth Memory (HBM) DRAM","key":"ref14"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ISSCC.2016.7418034"},{"key":"ref16","first-page":"1","article-title":"A field study of DRAM errors","author":"sridharan","year":"2012","journal-title":"Proc Int Conf High Perform Comput Netw Storage Anal"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1145\/2189750.2150989"},{"key":"ref18","first-page":"1","article-title":"Feng Shui of supercomputer memory: Positional effects in DRAM and SRAM faults","author":"sridharan","year":"2013","journal-title":"Proc Int Conf High Perform Comput Netw Storage Anal"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1145\/2694344.2694348"},{"year":"2004","author":"lin","journal-title":"Error Control Coding","key":"ref4"},{"key":"ref3","first-page":"1","article-title":"AMD&#x2019;s next generation GPU and high bandwidth memory architecture: FURY","author":"macri","year":"2015","journal-title":"Proc IEEE Hot Chips 27 Symp"},{"year":"1989","author":"rao","journal-title":"Error-control coding for computer systems","key":"ref6"},{"year":"2007","author":"jacob","journal-title":"Memory Systems Cache DRAM Disk","key":"ref5"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/2540708.2540717"},{"year":"2012","article-title":"White paper - AMD Graphics Cores Next (GCN) Architecture","key":"ref7"},{"doi-asserted-by":"publisher","key":"ref49","DOI":"10.1145\/2840807"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/IISWC.2016.7581276"},{"key":"ref46","first-page":"225","article-title":"Managing shared last-level cache in a heterogeneous multicore processor","author":"mekkat","year":"2013","journal-title":"Proc 22nd IEEE\/ACM Int Conf Parallel Architect Compilation Techn"},{"doi-asserted-by":"publisher","key":"ref45","DOI":"10.1109\/HPCA.2012.6168947"},{"doi-asserted-by":"publisher","key":"ref48","DOI":"10.1109\/MICRO.2014.62"},{"doi-asserted-by":"publisher","key":"ref47","DOI":"10.1109\/IISWC.2014.6983054"},{"doi-asserted-by":"publisher","key":"ref42","DOI":"10.1109\/IISWC.2010.5650274"},{"doi-asserted-by":"publisher","key":"ref41","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref44","first-page":"33","article-title":"CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory","author":"chen","year":"2012","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"doi-asserted-by":"publisher","key":"ref43","DOI":"10.1109\/L-CA.2011.4"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8683959\/08576671.pdf?arnumber=8576671","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:48:53Z","timestamp":1657745333000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8576671\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5,1]]},"references-count":49,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tc.2018.2886884","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2019,5,1]]}}}