{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:46:34Z","timestamp":1773193594569,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003052","name":"Ministry of Trade, Industry and Energy","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003052","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003052","name":"Ministry of Trade, Industry and Energy","doi-asserted-by":"publisher","award":["10080613"],"award-info":[{"award-number":["10080613"]}],"id":[{"id":"10.13039\/501100003052","id-type":"DOI","asserted-by":"publisher"}]},{"name":"DRAM\/PRAM heterogeneous memory architecture and controller IC design technology research and development"},{"DOI":"10.13039\/501100002553","name":"Seoul National University of Science and Technology","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002553","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2019,10,1]]},"DOI":"10.1109\/tc.2019.2907248","type":"journal-article","created":{"date-parts":[[2019,3,25]],"date-time":"2019-03-25T22:38:46Z","timestamp":1553553526000},"page":"1428-1441","source":"Crossref","is-referenced-by-count":26,"title":["An Effective DRAM Address Remapping for Mitigating Rowhammer Errors"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4142-3475","authenticated-orcid":false,"given":"Moonsoo","family":"Kim","sequence":"first","affiliation":[]},{"given":"Jungwoo","family":"Choi","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7962-657X","authenticated-orcid":false,"given":"Hyun","family":"Kim","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6811-9647","authenticated-orcid":false,"given":"Hyuk-Jae","family":"Lee","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830820"},{"key":"ref32","first-page":"117","article-title":"Can't touch this: Practical and generic software-only defenses against rowhammer attacks","author":"brasser","year":"2017","journal-title":"Proc 26th USENIX Security Symp"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2954679.2872390"},{"key":"ref30","article-title":"Thoughts on Intel Xeon e5&#x2013;2600 v2 product family performance optimisation&#x2013;component selection guidelines","author":"kaczmarski","year":"2014"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592000"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1109\/SP.2019.00089","article-title":"Exploiting correcting codes: On the effectiveness of ECC memory against rowhammer attacks","author":"cojocar","year":"2019"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062281"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2014.2332177"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2614497"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2002.994601"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.30"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750397"},{"key":"ref18","first-page":"565","article-title":"Drama: Exploiting DRAM addressing for cross-cpu attacks","author":"pessl","year":"2016","journal-title":"Proc Usenix Security Symp"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3152701.3152709"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2018.00031"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927156"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_15"},{"key":"ref29","first-page":"1","article-title":"Intel SGX explained","volume":"2016","author":"costanand","year":"2016","journal-title":"IACR Cryptology ePrint Archive"},{"key":"ref5","first-page":"1","article-title":"Flip feng shui: Hammering a needle in the software stack","author":"razavi","year":"2016","journal-title":"Proc Usenix Security Symp"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495576"},{"key":"ref7","first-page":"19","article-title":"One bit flips, one cloud flops: Cross-VM row hammer attacks and privilege escalation","author":"xiao","year":"2016","journal-title":"Proc Usenix Security Symp"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694348"},{"key":"ref9","first-page":"1675","article-title":"Drammer: Deterministic rowhammer attacks on mobile platforms","author":"fratantonio","year":"2016","journal-title":"Proc ACM SIGSAC Conf Comput Commun Security"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665726"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080242"},{"key":"ref22","author":"jacob","year":"2010","journal-title":"Memory Systems Cache DRAM Disk"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237032"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2018.09.004"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IVSW.2018.8494868"},{"key":"ref26","first-page":"22","article-title":"Cacti 6.0: A tool to model large caches","author":"muralimanohar","year":"2009","journal-title":"HP Laboratories"},{"key":"ref25","article-title":"DRAM scaling challenges and solutions in lpddr4 context","author":"kasamsetty","year":"2014"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8826662\/08673635.pdf?arnumber=8673635","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:07:17Z","timestamp":1657746437000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8673635\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10,1]]},"references-count":33,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tc.2019.2907248","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,10,1]]}}}