{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:56:23Z","timestamp":1780674983707,"version":"3.54.1"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"IT R&#x0026;D program of MOTIE\/KEIT"},{"DOI":"10.13039\/501100003052","name":"Ministry of Trade, Industry and Energy","doi-asserted-by":"publisher","award":["10080590"],"award-info":[{"award-number":["10080590"]}],"id":[{"id":"10.13039\/501100003052","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Korea Semiconductor Research Consortium"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2020,2,1]]},"DOI":"10.1109\/tc.2019.2944163","type":"journal-article","created":{"date-parts":[[2019,9,28]],"date-time":"2019-09-28T03:00:25Z","timestamp":1569639625000},"page":"158-171","source":"Crossref","is-referenced-by-count":4,"title":["Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache"],"prefix":"10.1109","volume":"69","author":[{"given":"Minsik","family":"Oh","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6334-122X","authenticated-orcid":false,"given":"Kwangsu","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Duheon","family":"Choi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2981-0800","authenticated-orcid":false,"given":"Hyuk-Jun","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2013-8763","authenticated-orcid":false,"given":"Eui-Young","family":"Chung","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1016\/j.jestch.2016.06.007"},{"key":"ref30","first-page":"247","article-title":"Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM","author":"lee","year":"2012","journal-title":"Proc IEEE Int SOC Conf"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081626"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333717"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2013.6629298"},{"key":"ref13","first-page":"183","article-title":"Energy-efficient exlusive last-level hybrid caches consisting of SRAM and STT-RAM","author":"kim","year":"2015","journal-title":"Proc IFIP Int Conf Very Large-Scale Integr"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2016.7479181"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2435772"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333708"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2014.7004174"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2689010"},{"key":"ref19","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","author":"wu","year":"2009","journal-title":"Proc Des Autom Test Europe Conf Exhib"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2620168"},{"key":"ref27","article-title":"CACTI 6.0: A tool to understand large caches","author":"muralimanohar","year":"2008"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835944"},{"key":"ref6","first-page":"175","article-title":"Sampling dead block prediction for last-level caches","author":"lhan","year":"2010","journal-title":"Proc 43rd Annu IEEE\/ACM Int Symp Microarchitecture"},{"key":"ref29","article-title":"Spin-transfer torque magnetic random access memory (STT-RAM)","volume":"9","author":"apalkov","year":"2013","journal-title":"ACM J Emerging Technol Comput Syst"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70816"},{"key":"ref8","first-page":"1092","article-title":"Prediction table based management policy for STT-RAM and SRAM hybrid cache","author":"quan","year":"2012","journal-title":"Proc 7th Int Conf Comput Convergence Technol"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835933"},{"key":"ref2","first-page":"847","article-title":"OAP: An obstruction-aware cache management policy for STT-RAM last-level caches","author":"want","year":"2013","journal-title":"Proc Des Autom Test Europe Conf Exhib"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993611"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840931"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2278295"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974658"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"2149","DOI":"10.1109\/TVLSI.2014.2361150","article-title":"High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy","volume":"23","author":"syu","year":"2015","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8959511\/08851211.pdf?arnumber=8851211","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:06:07Z","timestamp":1651068367000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8851211\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2,1]]},"references-count":31,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tc.2019.2944163","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,2,1]]}}}