{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T10:14:45Z","timestamp":1768817685963,"version":"3.49.0"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2021,4,1]]},"DOI":"10.1109\/tc.2019.2946365","type":"journal-article","created":{"date-parts":[[2019,10,8]],"date-time":"2019-10-08T20:00:04Z","timestamp":1570564804000},"page":"539-551","source":"Crossref","is-referenced-by-count":7,"title":["Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1867-1801","authenticated-orcid":false,"given":"Hoseok","family":"Seol","sequence":"first","affiliation":[{"name":"DRAM Development Division, Samsung, Hwasung, Gyeonggido, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4879-1262","authenticated-orcid":false,"given":"Minhye","family":"Kim","sequence":"additional","affiliation":[{"name":"Law School, Seoul National University (SNU), Seoul, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7440-2067","authenticated-orcid":false,"given":"Taesoo","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Computer Science, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9585-4591","authenticated-orcid":false,"given":"Yongdae","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lee-Sup","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750408"},{"key":"ref38","article-title":"Dram power model","year":"2010"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.54"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835956"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522355"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2737646"},{"key":"ref37","article-title":"Micron DDR4 SDRAM system-power calculator","year":"2016"},{"key":"ref36","article-title":"Memory Scheduling Championship (MSC)","year":"2012"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446093"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750402"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1752046.1752053"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139696463"},{"key":"ref11","first-page":"17","article-title":"TRESOR runs encryption securely outside ram","author":"m\u00fcller","year":"2011","journal-title":"Proc 20th USENIX Conf Security"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2076732.2076743"},{"key":"ref13","article-title":"Frozencache mitigating cold-boot attacks for full- disk-encryption software","author":"pabel","year":"2010","journal-title":"Proc 27th Chaos Commun Congr"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2014.23125"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.8"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2016.13"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2523649.2523656"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2566673"},{"key":"ref19","article-title":"8gb B-die DDR4 SDRAM samsung","year":"2015"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/4.839915"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ARES.2015.28"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2901318.2901320"},{"key":"ref3","article-title":"An in-depth analysis of the cold boot attack","author":"carbone","year":"2011"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-38980-1_23"},{"key":"ref29","first-page":"185","article-title":"RowClone: Fast and Energy-Efficient in-DRAM Bulk Data Copy and Initialization","author":"vivek seshadri","year":"2013","journal-title":"2013 46th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ARES.2013.52"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.diin.2016.01.009"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1186\/s13635-016-0041-4"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1506409.1506429"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.10"},{"key":"ref1","article-title":"Data remanence in semiconductor devices","author":"gutmann","year":"2001","journal-title":"Proc 20th USENIX Conf Security"},{"key":"ref46","article-title":"Intel atom processor s1200 product family for microserver","year":"2012"},{"key":"ref20","author":"jacob","year":"2008","journal-title":"Memory Systems (Cache DRAM Disk)"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000086"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2417540"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.80"},{"key":"ref21","article-title":"JEDEC standard : DDR4 SDRAM specification","year":"2012"},{"key":"ref42","first-page":"390","article-title":"23.2 a 5 gb\/s\/pin 8 Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme","author":"lee","year":"2017","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref24","article-title":"Micron technical note, TN-41&#x2013;07: DDR3 power-up, initialization, and reset","year":"2008"},{"key":"ref41","article-title":"4gb D-die DDR4 SDRAM samsung","year":"2014"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2014.2369041"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136502"},{"key":"ref26","article-title":"iPhone boot-up time comparison: 6s vs. 6 vs. 5s vs. 5 vs. 4 vs. 3gs","year":"2015"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379237"},{"key":"ref25","article-title":"Android vs iphone boot times tested: which one is the fastest?","year":"2015"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/9378888\/08862904.pdf?arnumber=8862904","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:05:33Z","timestamp":1642003533000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8862904\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,1]]},"references-count":47,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tc.2019.2946365","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,4,1]]}}}