{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T15:58:28Z","timestamp":1776182308734,"version":"3.50.1"},"reference-count":62,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1423302"],"award-info":[{"award-number":["CCF-1423302"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1527051"],"award-info":[{"award-number":["CNS-1527051"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2020,4,1]]},"DOI":"10.1109\/tc.2019.2959307","type":"journal-article","created":{"date-parts":[[2019,12,18]],"date-time":"2019-12-18T21:05:40Z","timestamp":1576703140000},"page":"577-590","source":"Crossref","is-referenced-by-count":18,"title":["Bufferless Network-on-Chips With Bridged Multiple Subnetworks for Deflection Reduction and Energy Savings"],"prefix":"10.1109","volume":"69","author":[{"given":"Xiyue","family":"Xiang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4410-793X","authenticated-orcid":false,"given":"Purushottam","family":"Sigdel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8357-6632","authenticated-orcid":false,"given":"Nian-Feng","family":"Tzeng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372638"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2786572.2786593"},{"key":"ref33","first-page":"11","article-title":"Deja vu switching for multiplane NoCs","author":"abousamra","year":"2012","journal-title":"Proc 6th IEEE\/ACM Int Symp Netw Chip"},{"key":"ref32","first-page":"73","article-title":"Flit-reservation flow control","author":"peh","year":"2000","journal-title":"Proc 6th Int Symp High-Performance Comput Architec"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492721"},{"key":"ref37","first-page":"458","article-title":"NoC Architectures for silicon interposer systems","author":"jerger","year":"2014","journal-title":"Proc of the 47th Intl Symp on Microarchitecture"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.15"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.129"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1145\/564870.564873"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488779"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798251"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/E3S.2013.6705860"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.22"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.10"},{"key":"ref21","article-title":"Adaptive cluster throttling: Improving high-load performance in bufferless on-chip networks","author":"ausavarungirun","year":"2011"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485950"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2342356.2342436"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/1868447.1868459"},{"key":"ref59","first-page":"1","article-title":"Realistic workload characterization and analysis for networks-on-chip design","author":"gratz","year":"2010","journal-title":"Proc Chip Multiprocessor Mem Syst Interconnects"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1147\/rd.492.0265"},{"key":"ref57","year":"0"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00049"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872414"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/3079079.3079090"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903256"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.29"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.19"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446076"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250681"},{"key":"ref13","author":"dally","year":"2003","journal-title":"Principles and Practices of Interconnection Networks"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1468075.1468121"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056048"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4484015"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2014.31"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717783"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2014.7008756"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749724"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310759"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.8"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669144"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134508"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898075"},{"key":"ref9","article-title":"CHIPPER: A low-complexity bufferless deflection router","author":"fallin","year":"2010"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2014.31"},{"key":"ref45","article-title":"An Introduction to the intel quickpath Interconnect","year":"0"},{"key":"ref48","first-page":"9","article-title":"HAT: Heterogeneous adaptive throttling for on-chip networks","author":"chang","year":"2014","journal-title":"Proc 24th Int Symp Comput Architecture High Perform Comput"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2016.01.009"},{"key":"ref42","article-title":"AMBA: The standard for on-chip communication","year":"0"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665680"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.43"},{"key":"ref43","article-title":"AMBA AXI and ACE Protocol Specification","year":"0"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/12\/9032251\/8936414-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/9032251\/08936414.pdf?arnumber=8936414","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:16:13Z","timestamp":1651068973000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8936414\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4,1]]},"references-count":62,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tc.2019.2959307","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4,1]]}}}