{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T07:44:53Z","timestamp":1767771893556,"version":"3.37.3"},"reference-count":56,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2020,5,1]]},"DOI":"10.1109\/tc.2020.2964671","type":"journal-article","created":{"date-parts":[[2020,1,7]],"date-time":"2020-01-07T21:04:45Z","timestamp":1578431085000},"page":"734-748","source":"Crossref","is-referenced-by-count":19,"title":["Crossbar-Constrained Technology Mapping for ReRAM Based In-Memory Computing"],"prefix":"10.1109","volume":"69","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6561-8934","authenticated-orcid":false,"given":"Debjyoti","family":"Bhattacharjee","sequence":"first","affiliation":[]},{"given":"Yaswanth","family":"Tavva","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9628-3847","authenticated-orcid":false,"given":"Arvind","family":"Easwaran","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8818-6983","authenticated-orcid":false,"given":"Anupam","family":"Chattopadhyay","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"1420","article-title":"Simulation of TaO$_x$x-based complementary resistive switches by a physics-based memristive model","author":"siemon","year":"2014","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927095"},{"key":"ref33","first-page":"427","article-title":"The programmable logic-in-memory (PLiM) computer","author":"gaillardon","year":"2016","journal-title":"Proc Design Autom Test Eur Conf Exhib"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858298"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967020"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081665"},{"key":"ref37","first-page":"225","article-title":"SIMPLE MAGIC: Synthesis and in-memory mapping of logic execution for memristor-aided logic","author":"hur","year":"2017","journal-title":"Proc 36th Int Conf Comput -Aided Design"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2763171"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2570248"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897985"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1049\/el.2010.3407"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2009.5226356"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001393"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124553"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2723372.2764942"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms15199"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2017.83"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1039\/C6NR08024C"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1038\/srep36652"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2017.2719161"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1038\/srep05780"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-017-18329-3"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1995.528817"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1995.470414"},{"journal-title":"Approximation Algorithms","year":"2013","author":"vazirani","key":"ref56"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342237"},{"key":"ref54","first-page":"948","article-title":"Fast Logic Synthesis for RRAM-Based in-Memory Computing Using Majority-Inverter Graphs","author":"saeideh shirinzadeh","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/12.795226"},{"key":"ref52","first-page":"250","article-title":"Minimum polynomial implementation of systems of incompletely specified Boolean functions","author":"zakrevskij","year":"1995","journal-title":"Proc IFIP WG 10 5 Workshop Applicat Reed-Muller Expansion"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2012.6213638"},{"key":"ref11","first-page":"153","article-title":"Multi-layer sidewall WOX resistive memory suitable for 3D ReRAM","author":"chien","year":"2012","journal-title":"Proc Symp VLSI Technol"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/CNNA.2012.6331466"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2778113"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"403","DOI":"10.1038\/nmat2748","article-title":"Complementary resistive switches for passive nanocrossbar memories","volume":"9","author":"linn","year":"2010","journal-title":"Nature Mater"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2398217"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2016.7753568"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2017.7918336"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-54840-1_13"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-016-1608-8"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1021\/nl203687n"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750386"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001159"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/22\/48\/485203"},{"key":"ref7","article-title":"Genome read in-memory (GRIM) filter: Fast location filtering in DNA read mapping using emerging memory technologies","author":"kim","year":"2017","journal-title":"Pacific Symp Biocomputing"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-1385-4"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"625","DOI":"10.1038\/nmat3070","article-title":"A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5- x\/TaO2- x bilayer structures","volume":"10","author":"leeetal","year":"2011","journal-title":"Nature Mater"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488484"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.860955"},{"year":"2017","key":"ref48"},{"key":"ref47","first-page":"242","article-title":"Fast heuristic minimization of exclusive-sums-of-products","author":"mishchenko","year":"2001","journal-title":"Proc Reed-Muller Workshop"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"ref41","doi-asserted-by":"crossref","first-page":"8166","DOI":"10.1021\/nn3028776","article-title":"High current density and nonlinearity combination of selection device based on $TaO_x\/TiO_2\/TaO_x$TaOx\/TiO2\/TaOx structure for one selector&#x2013;one resistor arrays","volume":"6","author":"leeetal","year":"2012","journal-title":"ACS Nano"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173171"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/23\/30\/305205"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/9058928\/08951116.pdf?arnumber=8951116","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:16:13Z","timestamp":1651068973000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8951116\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5,1]]},"references-count":56,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tc.2020.2964671","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2020,5,1]]}}}