{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T08:21:35Z","timestamp":1761294095171,"version":"3.37.3"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002322","name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","doi-asserted-by":"publisher","award":["001"],"award-info":[{"award-number":["001"]}],"id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2021,1,1]]},"DOI":"10.1109\/tc.2020.2984736","type":"journal-article","created":{"date-parts":[[2020,4,2]],"date-time":"2020-04-02T21:31:03Z","timestamp":1585863063000},"page":"83-98","source":"Crossref","is-referenced-by-count":11,"title":["Multi-Target Adaptive Reconfigurable Acceleration for Low-Power IoT Processing"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0012-7023","authenticated-orcid":false,"given":"Marcelo","family":"Brandalero","sequence":"first","affiliation":[{"name":"Brandenburg University of Technology Cottbus-Senftenberg (B-TU), Cottbus, Germany"}]},{"given":"Luigi","family":"Carro","sequence":"additional","affiliation":[{"name":"Instituto de Informática at Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4492-1747","authenticated-orcid":false,"given":"Antonio Carlos Schneider","family":"Beck","sequence":"additional","affiliation":[{"name":"Instituto de Informática at Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2607-8135","authenticated-orcid":false,"given":"Muhammad","family":"Shafique","sequence":"additional","affiliation":[{"name":"Institute of Computer Engineering, Vienna University of Technology (TU Wien), Vienna, Austria"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717783"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref33","first-page":"213","article-title":"Using dynamic binary translation to fuse dependent instructions","author":"hu","year":"2004","journal-title":"Proc Int Symp Code Generation Optim"},{"key":"ref32","first-page":"260","article-title":"Lazy superscalar","author":"a??l?o?lu","year":"2015","journal-title":"Proc 42nd Annu Int Symp Comput Archit"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351595"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696325"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2013.6662519"},{"article-title":"The rocket chip generator","year":"2016","author":"asanovi?","key":"ref36"},{"article-title":"The berkeley out-of-order machine (BOOM): An industry-competitive, synthesizable, parameterized RISC-V processor","year":"2015","author":"celio","key":"ref35"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105745"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522348"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.94"},{"key":"ref11","first-page":"1","article-title":"Voltage island management in near threshold manycore architectures to mitigate dark silicon","author":"silvano","year":"2014","journal-title":"Proc Des Autom Test Eur Conf Exhibit"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2003.1191529"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.30"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1145\/384286.264126","article-title":"DAISY: Dynamic compilation for 100% architectural compatibility","author":"ebcio?lu","year":"1997","journal-title":"Proc Int Symp Comput Archit"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3173456"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927147"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2864288"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142986"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391486"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.54"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2821510"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2630303"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2342509.2342513"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2016.7818353"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283789"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715121"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2717782"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446104"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2014.6894411"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.5"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446060"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2014.03.004"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2012.6263951"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927223"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035453"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750414"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref26","article-title":"Near-threshold voltage (NTV) design - opportunities and challenges","author":"kaul","year":"2012","journal-title":"Proc Des Aut Conf DAC"},{"year":"2017","key":"ref43","article-title":"IRDSTM 2017: More Moore"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/4.881202"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/9290453\/09054992.pdf?arnumber=9054992","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,3]],"date-time":"2022-11-03T21:27:16Z","timestamp":1667510836000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9054992\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,1]]},"references-count":45,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tc.2020.2984736","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2021,1,1]]}}}