{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T23:49:24Z","timestamp":1783036164917,"version":"3.54.6"},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2021,4,1]]},"DOI":"10.1109\/tc.2020.2994067","type":"journal-article","created":{"date-parts":[[2020,5,11]],"date-time":"2020-05-11T15:39:30Z","timestamp":1589211570000},"page":"640-654","source":"Crossref","is-referenced-by-count":20,"title":["ECC-United Cache: Maximizing Efficiency of Error Detection\/Correction Codes in Associative Cache Memories"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4204-9131","authenticated-orcid":false,"given":"Hamed","family":"Farbeh","sequence":"first","affiliation":[{"name":"Department of Computer Engineering, Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7304-7729","authenticated-orcid":false,"given":"Leila","family":"Delshadtehrani","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Boston University, Boston, MA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3695-8216","authenticated-orcid":false,"given":"Hyeonggyu","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5106-8409","authenticated-orcid":false,"given":"Soontae","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Computing, KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.174"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013273"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654109"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"884","DOI":"10.1109\/TDMR.2014.2332364","article-title":"A method to design SEC-DED-DAEC codes with optimized decoding","volume":"14","author":"sanchez-macian","year":"2014","journal-title":"IEEE Trans Device Mater Rel"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669126"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2595570"},{"key":"ref35","first-page":"461","article-title":"Energy-efficient cache design using variable-strength error-correcting codes","author":"alameldeen","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378699"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2226585"},{"key":"ref27","first-page":"349","article-title":"Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code","author":"saiz-adalid","year":"0","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1049\/el.2013.2897"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2874467"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8467758"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2557326"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/EDCC.2014.25"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2628742"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2186965"},{"key":"ref23","first-page":"499","article-title":"Choosing an error protection scheme for a microprocessor&#x2019;s L1 data cache","author":"sadler","year":"2007","journal-title":"Proc Int Conf Comput Des"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2204753"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2019.8758647"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2770874"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2319291"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DSN-W.2018.00048"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2014.6873660"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2544811"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2232671"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.117"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714946"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2701880"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287686"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342194"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2017.2706263"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555771"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194570"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.203"},{"key":"ref8","first-page":"1","article-title":"Enhanced error correction against multiple-bit-upset based on BCH code for SRAM","author":"ma","year":"2013","journal-title":"Proc IEEE 10th Int Conf ASIC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2303856"},{"key":"ref49","article-title":"Design compiler user guide","year":"2010"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2010.2043265"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2177458"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2019.05.020"},{"key":"ref48","article-title":"CACTI 6.0: A tool to model large caches","author":"muralimanohar","year":"2009"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000091"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2111469"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2014.2332616"},{"key":"ref44","first-page":"1","article-title":"PSP-cache: A low-cost fault-tolerant cache memory architecture","author":"farbeh","year":"2014","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2875439"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/9378888\/09091307.pdf?arnumber=9091307","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:51:12Z","timestamp":1641988272000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9091307\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,1]]},"references-count":50,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tc.2020.2994067","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,4,1]]}}}