{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T14:24:35Z","timestamp":1772115875884,"version":"3.50.1"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"NSF\/SRC E2CDA, ASCENT"},{"name":"SRC\/DARPA JUMP research centers"},{"name":"SONY research"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2020,8,1]]},"DOI":"10.1109\/tc.2020.3000218","type":"journal-article","created":{"date-parts":[[2020,6,5]],"date-time":"2020-06-05T20:44:21Z","timestamp":1591389861000},"page":"1113-1127","source":"Crossref","is-referenced-by-count":57,"title":["Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses"],"prefix":"10.1109","volume":"69","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8239-0492","authenticated-orcid":false,"given":"Yandong","family":"Luo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0068-3652","authenticated-orcid":false,"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","article-title":"The NVIDIA titan V deep learning deep dive: It's all about the tensor cores","author":"oh","year":"2018"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124545"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2943047"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702715"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2789723"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510648"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.5402\/2012\/916259"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317872"},{"key":"ref35","first-page":"210","article-title":"Integration of 28nm MJT for 8?16Gb level MRAM with full investigation of thermal stability","author":"kim","year":"2011","journal-title":"Proc Symp VLSI Technol"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838491"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2824304"},{"key":"ref40","article-title":"Tearing Apart Google's TPU 3.0 AI coprocessor","author":"teich","year":"2018"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref12","first-page":"388","article-title":"24.1 A 1Mb Multibit ReRAM computing-in-memory macro with 14.6ns parallel MAC computing time for CNN based AI edge processors","author":"xue","year":"2019","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409625"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614611"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310392"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662444"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372570"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2933148"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-018-0180-5"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3354265.3354266"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310401"},{"key":"ref27","article-title":"Dorefa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients","author":"zhou","year":"0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196071"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001177"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2019.2925061"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838029"},{"key":"ref22","article-title":"Training and inference with integers in deep neural networks","author":"wu","year":"2018"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045288"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510690"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2019.2934050"},{"key":"ref41","year":"0"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993491"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1021\/nl904092h"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351656"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2016.2582859"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3357526.3357552"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/12\/9136938\/9109723-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/9136938\/09109723.pdf?arnumber=9109723","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:09:57Z","timestamp":1651068597000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9109723\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8,1]]},"references-count":45,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tc.2020.3000218","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,8,1]]}}}