{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:01:54Z","timestamp":1781884914613,"version":"3.54.5"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2021,11,1]]},"DOI":"10.1109\/tc.2020.3034400","type":"journal-article","created":{"date-parts":[[2020,10,28]],"date-time":"2020-10-28T19:46:58Z","timestamp":1603914418000},"page":"2001-2012","source":"Crossref","is-referenced-by-count":19,"title":["LPC: An Error Correction Code for Mitigating Faults in 3D Memories"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4306-3573","authenticated-orcid":false,"given":"David C. C.","family":"Freitas","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David F. M.","family":"Mota","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7811-7896","authenticated-orcid":false,"given":"Cesar","family":"Marcon","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2590-9520","authenticated-orcid":false,"given":"Jarbas A. N.","family":"Silveira","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joao C. M.","family":"Mota","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2766361"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2368262"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2020.113582"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/S0045-7906(99)00034-8"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2837220"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-011-9078-2"},{"key":"ref37","first-page":"1","article-title":"Protecting SRAM-based FPGAs against multiple bit upsets using erasure codes","author":"rao","year":"2014","journal-title":"Proc ACM\/EDAC\/IEEE Des Automat Conf"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"2433","DOI":"10.1109\/TNS.2005.860675","article-title":"Investigation of multi-bit upsets in a 150nm technology SRAM device","volume":"52","author":"radaelli","year":"2005","journal-title":"IEEE Trans Nucl Sci"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2019.00017"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001174"},{"key":"ref10","first-page":"1","article-title":"On-chip checkpoint with 3D-stacked memories","author":"sato","year":"2015","journal-title":"Proc Int Conf 3D Syst Integr"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.29"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.92"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2015.7315128"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2801856"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2018.2886401"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2018.2878911"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2015.15.5.445"},{"key":"ref17","first-page":"1","article-title":"Area and reliability efficient ECC scheme for 3D RAMs","author":"chang","year":"2012","journal-title":"Proc VLSI Des Autom Test"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317805"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446094"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1976.4328569"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.57"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1976.4328568"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1979.4330219"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2019.00048"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1977.4329194"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1976.4328569"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2019.2900629"},{"key":"ref2","first-page":"435","article-title":"Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology","author":"zhang","year":"2009","journal-title":"Proc IEEE\/ACM Int Symp Microarchit"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1977.4329194"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2777887"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-018-5738-5"},{"key":"ref22","first-page":"568","volume":"16","author":"macwilliams","year":"1977","journal-title":"The Theory of Error-Correcting Codes"},{"key":"ref21","first-page":"41","author":"tocci","year":"2007","journal-title":"Digital Systems &#x2013; Principles Applications"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1002\/0470035706"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1002\/0471739219"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000091"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/9562753\/09242293.pdf?arnumber=9242293","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,2,21]],"date-time":"2022-02-21T22:02:33Z","timestamp":1645480953000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9242293\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,1]]},"references-count":40,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tc.2020.3034400","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,11,1]]}}}