{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:15:14Z","timestamp":1766067314766,"version":"3.37.3"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2021,6,1]]},"DOI":"10.1109\/tc.2021.3069968","type":"journal-article","created":{"date-parts":[[2021,3,31]],"date-time":"2021-03-31T19:51:16Z","timestamp":1617220276000},"page":"892-905","source":"Crossref","is-referenced-by-count":8,"title":["Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty"],"prefix":"10.1109","volume":"70","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8912-9657","authenticated-orcid":false,"given":"Abhijit","family":"Das","sequence":"first","affiliation":[]},{"given":"Abhishek","family":"Kumar","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0314-8778","authenticated-orcid":false,"given":"John","family":"Jose","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3129-0664","authenticated-orcid":false,"given":"Maurizio","family":"Palesi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI49217.2020.00036"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2907909"},{"key":"ref33","first-page":"1","article-title":"Leveraging on-chip networks for efficient prediction on multicore coherence","author":"huang","year":"2014","journal-title":"Proc Design Automation Test Eur Conf Exhib"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.52"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-92990-1_27"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.27"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045570"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317799"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898020"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2773061"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898075"},{"key":"ref40","first-page":"230","article-title":"Reducing off-chip miss penalty by exploiting underutilised on-chip router buffers","author":"das","year":"2020","journal-title":"Proc IEEE 38th Int Conf Comput Des"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.10"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437683"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676939"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2567936"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.1"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"year":"2017","key":"ref19"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref4","first-page":"1","article-title":"Realistic workload characterization and analysis for networks-on-chip design","author":"gratz","year":"2010","journal-title":"Proc 4th Workshop Chip Multiprocessor Memory Syst Interconnects"},{"year":"2017","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306792"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1736065.1736069"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/74925.74944"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.23"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872414"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"year":"2017","key":"ref2"},{"key":"ref9","first-page":"25","article-title":"Scorpio: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering","author":"daya","year":"2014","journal-title":"Proc ACM\/IEEE 41st Int Symp Comput Archit"},{"year":"2015","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2827928"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927052"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/MCE.2021.3062001"},{"key":"ref23","first-page":"97","article-title":"DAMQ self-compacting buffer schemes for systems with network-on-chip","author":"liu","year":"2005","journal-title":"Proc Int Conf Comput Des"},{"article-title":"Write buffer","year":"1989","author":"mills jr and","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/325096.325162"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/9437243\/09392359.pdf?arnumber=9392359","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T08:52:14Z","timestamp":1643187134000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9392359\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,1]]},"references-count":41,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tc.2021.3069968","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2021,6,1]]}}}