{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T23:45:46Z","timestamp":1780443946061,"version":"3.54.1"},"reference-count":60,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100002398","name":"Sharif University of Technology","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002398","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/tc.2021.3082004","type":"journal-article","created":{"date-parts":[[2021,5,24]],"date-time":"2021-05-24T19:55:36Z","timestamp":1621886136000},"page":"1-1","source":"Crossref","is-referenced-by-count":16,"title":["3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison"],"prefix":"10.1109","author":[{"given":"Elham","family":"Cheshmikhani","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hamed","family":"Farbeh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hossein","family":"Asadi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2557326"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-13-8379-3_1"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2019.2923258"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2701880"},{"issue":"1","key":"ref5","first-page":"54","article-title":"STT-MRAM scaling and retention failure","volume":"17","author":"Naeimi","year":"2013","journal-title":"Intel Technol. J."},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287686"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3014361"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714946"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2689010"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2645207"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035342"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2881175"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.07.001"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2530883"},{"key":"ref15","volume-title":"Intel Arria 10 Hard Processor System Technical Reference Manual","year":"2017"},{"key":"ref16","volume-title":"ARM Cortex-A57 MPCore Processor, Technical Reference Manual","year":"2013"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.28"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2017.2706263"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2913207"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744908"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2010.5488324"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref23","volume-title":"Computer Systems: A Programmer\u2019s Perspective","author":"Bryant","year":"2016"},{"key":"ref24","volume-title":"64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)","year":"2009"},{"key":"ref25","volume-title":"AMD64 Architecture Programmer\u2019s Manual, Volume 2: System Programming","year":"2018"},{"key":"ref26","volume-title":"Intel 64 and IA-32 Architectures Software Developers Manual, Volume 1: Basic Architecture","year":"2016"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2875439"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2934685"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/EDCC.2016.10"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3321693"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2530883"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2016.05.005"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116444"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.56"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2009.2024325"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2012.2194790"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2412960"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1018"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MOCAST.2019.8741642"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2019.03.011"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-019-02758-0"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2996191"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2019.2905523"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/3357526.3357533"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-12-813353-8.00001-4"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1996.501190"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313948"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378636"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/1061267.1061270"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2015.16"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2906872"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TENCON.2006.344197"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2004.1260922"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2006.55"},{"key":"ref56","article-title":"Arm Cortex-A35 Processor","year":"2019","journal-title":"Technical Reference Manual"},{"key":"ref57","volume-title":"Technical Reference Manual,","year":"2017"},{"key":"ref58","volume-title":"Technical Reference Manual","year":"2019"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2625245"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974666"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/4358213\/09439871.pdf?arnumber=9439871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,9]],"date-time":"2024-01-09T23:20:28Z","timestamp":1704842428000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9439871\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":60,"URL":"https:\/\/doi.org\/10.1109\/tc.2021.3082004","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}