{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,7]],"date-time":"2025-08-07T20:54:23Z","timestamp":1754600063474},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004837","name":"Ministerio de Ciencia e Innovacin","doi-asserted-by":"publisher","award":["PID2019-107255GB-C22"],"award-info":[{"award-number":["PID2019-107255GB-C22"]}],"id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002809","name":"Generalitat de Catalunya","doi-asserted-by":"publisher","award":["2014-SGR-1051 and 2014-SGR-1272"],"award-info":[{"award-number":["2014-SGR-1051 and 2014-SGR-1272"]}],"id":[{"id":"10.13039\/501100002809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Mont-Blanc 2020","award":["779877"],"award-info":[{"award-number":["779877"]}]},{"name":"European Unions Horizon 2020"},{"name":"Spanish Ministry of Economy Industry and Competitiveness","award":["FJCI-2016- 30984","RYC-2016-21104"],"award-info":[{"award-number":["FJCI-2016- 30984","RYC-2016-21104"]}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2022]]},"DOI":"10.1109\/tc.2022.3174545","type":"journal-article","created":{"date-parts":[[2022,5,12]],"date-time":"2022-05-12T19:35:13Z","timestamp":1652384113000},"page":"1-1","source":"Crossref","is-referenced-by-count":1,"title":["Adaptive Power Shifting for Power-Constrained Heterogeneous Systems"],"prefix":"10.1109","author":[{"given":"Cristobal","family":"Ortega","sequence":"first","affiliation":[{"name":"Computer Science, Centro Nacional de Supercomputacion, 132144 Barcelona, Barcelona, Spain, 08034"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lluc","family":"Alvarez","sequence":"additional","affiliation":[{"name":"Computer Sciences, Barcelona Supercomputing Center, Barcelona, Catalunya, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alper","family":"Buyuktosunoglu","sequence":"additional","affiliation":[{"name":"Efficient and Resilient Systems, IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 10598"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramon","family":"Bertran Monfort","sequence":"additional","affiliation":[{"name":"Reliability- and Power-Aware Microarchitectures, IBM Reasearch, Yorktown Heights, New York, United States, 10598"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Todd Jon","family":"Rosedahl","sequence":"additional","affiliation":[{"name":"V9K, IBM, Rochester, Minnesota, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pradip","family":"Bose","sequence":"additional","affiliation":[{"name":"Computer Architecture, IBM-TJW Research Center H2-B48, Yorktown Heights, New York, United States, 10598"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miquel","family":"Moreto Planas","sequence":"additional","affiliation":[{"name":"Computer Sciences, Barcelona Supercomputing Center, Barcelona, Catalunya, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","volume-title":"Proc. 38th Annu. Int. Symp. Comput. Archit.","author":"Esmaeilzadeh"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.77"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1039"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.57"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056026"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771801"},{"key":"ref8","first-page":"29","article-title":"Scalable thread scheduling and global power management for heterogeneous many-core architectures","volume-title":"Proc. 19th Int. Conf. Parallel Archit. Compilation Techn.","author":"Winter"},{"key":"ref9","first-page":"175","article-title":"Pack & cap: Adaptive DVFS and thread packing under power caps","volume-title":"Proc. 44th Annu. IEEE\/ACM Int. Symp. Microarchitecture","author":"Cochran"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.59"},{"key":"ref11","first-page":"210","article-title":"Crank it up or dial it down: Coordinated multiprocessor frequency and folding control","volume-title":"Proc. 46th Annu. IEEE\/ACM Int. Symp. Microarchitecture","author":"Vega"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872375"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICEAC.2010.5702288"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2014.46"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657064"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.34"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2015.7054182"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485947"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503227"},{"key":"ref21","first-page":"401","article-title":"Workload and power budget partitioning for single-chip heterogeneous processors","volume-title":"Proc. 21st Int. Conf. Parallel Archit. Compilation Techn.","author":"Wang"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-67630-2_21"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2873584"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358285"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522310"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088188"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.22"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926260"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.12"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993657"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2976739"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2616339"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056029"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2016.7482074"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref37","first-page":"265","article-title":"TensorFlow: Large-scale machine learning on heterogeneous systems","volume-title":"Proc. 12th USENIX Conf. Oper. Syst. Des. Implementation","author":"Abadi"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835926"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00049"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872382"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.32"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.40"},{"key":"ref43","article-title":"The new linux perf tools","author":"de Melo","year":"2010"},{"key":"ref45","article-title":"The OpenMP implementation of NAS parallel benchmarks and its performance","author":"Jin","year":"1999"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.308"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/4358213\/09773997.pdf?arnumber=9773997","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,22]],"date-time":"2024-01-22T23:13:59Z","timestamp":1705965239000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9773997\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/tc.2022.3174545","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022]]}}}