{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T04:54:23Z","timestamp":1769835263268,"version":"3.49.0"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62002279"],"award-info":[{"award-number":["62002279"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Natural Science Basic Research Program of Shaanxi","award":["2020JQ-077"],"award-info":[{"award-number":["2020JQ-077"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2023,10]]},"DOI":"10.1109\/tc.2023.3271060","type":"journal-article","created":{"date-parts":[[2023,4,27]],"date-time":"2023-04-27T17:46:39Z","timestamp":1682617599000},"page":"2795-2807","source":"Crossref","is-referenced-by-count":2,"title":["DHTS: A Dynamic Hybrid Tiling Strategy for Optimizing Stencil Computation on GPUs"],"prefix":"10.1109","volume":"72","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7120-894X","authenticated-orcid":false,"given":"Song","family":"Liu","sequence":"first","affiliation":[{"name":"School of Computer Science and Technology, Xi&#x0027;an Jiaotong University, Shaanxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1643-4191","authenticated-orcid":false,"given":"Zengyuan","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Computer Science and Technology, Xi&#x0027;an Jiaotong University, Shaanxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8699-9115","authenticated-orcid":false,"given":"Weiguo","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Computer Science and Technology, Xi&#x0027;an Jiaotong University, Shaanxi, China"}]}],"member":"263","reference":[{"key":"ref13","first-page":"66","article-title":"Hybrid hexagonal\/classical tiling for GPUs","author":"grosser","year":"2014","journal-title":"Proc IEEE\/ACM 12th Int Symp Code Gener Optim"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3368826.3377904"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259044"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3295500.3356210"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626414410023"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/s00224-007-9098-2"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-021-03835-z"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/SFFCS.1999.814600"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2400682.2400713"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-019-1919-7"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1996.0075"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3469030"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1273442.1250761"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2019.00073"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3472456.3473517"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2017.10.041"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2012.107"},{"key":"ref39","article-title":"NVIDIA Kepler GK110 architecture whitepaper","year":"2012"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2458523.2458526"},{"key":"ref38","article-title":"NVIDIA Fermi architecture whitepaper","year":"2010"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088197"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2615094"},{"key":"ref24","first-page":"100","article-title":"High performance stencil code generation with lift","author":"hagedorn","year":"2018","journal-title":"Proc IEEE\/ACM 16th Int Symp Code Gener Optim"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-04580-6_7"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3528425.3529103"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2862896"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3352813"},{"key":"ref41","article-title":"NVIDIA Turing architecture whitepaper","year":"2018"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056781"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2778161"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3447818.3460369"},{"key":"ref27","first-page":"101","article-title":"A practical and fully automatic polyhedral program optimization system","author":"bondhugula","year":"2008","journal-title":"Proc 29th ACM SIGPLAN Conf Prog Lang Des Implement"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3447818.3462213"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626412500107"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-4337-4"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2015.7054196"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TGRS.2021.3078626"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3369382"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-12-410511-9.00003-4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-25636-4_16"},{"key":"ref40","article-title":"NVIDIA volta architecture whitepaper","year":"2017"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/10243393\/10109884.pdf?arnumber=10109884","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,2]],"date-time":"2023-10-02T17:50:29Z","timestamp":1696269029000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10109884\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10]]},"references-count":41,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tc.2023.3271060","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,10]]}}}