{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,5]],"date-time":"2026-02-05T09:39:12Z","timestamp":1770284352840,"version":"3.49.0"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000266","name":"EPSRC","doi-asserted-by":"publisher","award":["EP\/P010040\/1"],"award-info":[{"award-number":["EP\/P010040\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000266","name":"EPSRC","doi-asserted-by":"publisher","award":["EP\/R006865\/1"],"award-info":[{"award-number":["EP\/R006865\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2023,11,1]]},"DOI":"10.1109\/tc.2023.3292590","type":"journal-article","created":{"date-parts":[[2023,7,13]],"date-time":"2023-07-13T17:21:12Z","timestamp":1689268872000},"page":"3300-3313","source":"Crossref","is-referenced-by-count":3,"title":["Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets"],"prefix":"10.1109","volume":"72","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2791-2555","authenticated-orcid":false,"given":"Jianyi","family":"Cheng","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Imperial College London, London, U.K."}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6201-7447","authenticated-orcid":false,"given":"Estibaliz","family":"Fraca","sequence":"additional","affiliation":[{"name":"Department of Computer Science, University College London, London, U.K."}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6735-5533","authenticated-orcid":false,"given":"John","family":"Wickerson","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Imperial College London, London, U.K."}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0201-310X","authenticated-orcid":false,"given":"George A.","family":"Constantinides","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Imperial College London, London, U.K."}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375314"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/5.24143"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s10626-011-0116-9"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.3390\/electronics7120448"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.3182\/20100830-3-DE-4013.00006"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48745-X_8"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/32.214828"},{"key":"ref36","first-page":"197","article-title":"Shrink it or shed it! Minimize the use of LSQs in dataflow designs","author":"josipovi?","year":"0","journal-title":"Proc IEEE Int Conf Field-Program Technol (ICFPT)"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/COASE.2006.326847"},{"key":"ref30","author":"david","year":"2004","journal-title":"Discrete Continuous and Hybrid Petri Nets"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-30528-9_6"},{"key":"ref33","first-page":"135","article-title":"A structural encoding technique for the synthesis of asynchronous circuits","volume":"50","author":"carmona","year":"2002","journal-title":"Fundamenta Informaticae"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-22110-1_47"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TSMC.2022.3232743"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174264"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2014.7478841"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691121"},{"key":"ref39","first-page":"1192","article-title":"CHStone: A benchmark program suite for practical C-based high-level synthesis","author":"hara","year":"0","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2514740"},{"key":"ref38","volume":"437","author":"pouchet","year":"2012","journal-title":"PolyBench The Polyhedral Benchmark Suite"},{"key":"ref19","article-title":"Compiling Occam into field-programmable gate arrays","author":"page","year":"0","journal-title":"FPGAs Oxford Workshop on Field Programmable Logic and Applications"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927490"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1991.176748"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2480849"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/92.736132"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19951516"},{"key":"ref20","year":"2005","journal-title":"Handel C"},{"key":"ref42","year":"2020","journal-title":"Libchaos"},{"key":"ref41","year":"2020","journal-title":"Levenberg-maquardt-example"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3126525"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/43.945302"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337441"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887923"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM51124.2021.00031"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3065902"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375297"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502362"},{"key":"ref4","year":"2022","journal-title":"Intel® High Level Synthesis Compiler"},{"key":"ref3","year":"2022","journal-title":"Vitis High-Level Synthesis User Guide (UG1399)"},{"key":"ref6","year":"2022","journal-title":"Catapult High-Level Synthesis"},{"key":"ref5","year":"2022","journal-title":"Stratus High-Level Synthesis"},{"key":"ref40","year":"2020","journal-title":"LosAlamosChessEngine"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/10274758\/10183831.pdf?arnumber=10183831","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,30]],"date-time":"2023-10-30T18:55:20Z","timestamp":1698692120000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10183831\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11,1]]},"references-count":42,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tc.2023.3292590","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,11,1]]}}}