{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:33:18Z","timestamp":1772724798586,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2023,12,1]],"date-time":"2023-12-01T00:00:00Z","timestamp":1701388800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,12,1]],"date-time":"2023-12-01T00:00:00Z","timestamp":1701388800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,12,1]],"date-time":"2023-12-01T00:00:00Z","timestamp":1701388800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2023,12]]},"DOI":"10.1109\/tc.2023.3307796","type":"journal-article","created":{"date-parts":[[2023,8,23]],"date-time":"2023-08-23T17:56:20Z","timestamp":1692813380000},"page":"3561-3575","source":"Crossref","is-referenced-by-count":22,"title":["MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory"],"prefix":"10.1109","volume":"72","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5772-6377","authenticated-orcid":false,"given":"Samuel","family":"Riedel","sequence":"first","affiliation":[{"name":"Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9199-1708","authenticated-orcid":false,"given":"Matheus","family":"Cavalcante","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8776-5158","authenticated-orcid":false,"given":"Renzo","family":"Andri","sequence":"additional","affiliation":[{"name":"Independent Researcher, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8068-3806","authenticated-orcid":false,"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology, Zurich, Switzerland"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2016.7500697"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1002\/9781119818298.ch2"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HCS52781.2021.9566904"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.3045564"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref11","article-title":"GAP9 next generation processor for hearables and smart sensors","year":"2021"},{"key":"ref10","article-title":"Ampere®Altra®64-bit multi-core processor features","year":"0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1093\/bib\/bbq015"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3511094"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2185520.2185528"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474087"},{"key":"ref19","article-title":"ISA extensions in the Snitch processor for signal processing","author":"mazzola","year":"2021","journal-title":"Master’s thesis Politecnico di Torino"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3027900"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2018.2814602"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638459"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.022071133"},{"key":"ref20","author":"dally","year":"2004","journal-title":"Principles and Practices of Interconnection Networks"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643546"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3329930"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.36"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2014.7094761"},{"key":"ref8","article-title":"Apple unveils M1 Ultra, the world's most powerful chip for a personal computer","year":"2022"},{"key":"ref7","author":"hennessy","year":"2017","journal-title":"Computer Architecture A Quantitative Approach"},{"key":"ref9","article-title":"Intel® core™ i9-12900KS processor","year":"2022"},{"key":"ref4","article-title":"NVIDIA H100 tensor core GPU architecture","year":"2022"},{"key":"ref3","article-title":"Microprocessor trend data","author":"rupp","year":"0"},{"key":"ref6","first-page":"1","article-title":"Pixel Visual Core: Google's fully programmable image, vision, and AI processor for mobile devices","author":"redgrave","year":"0","journal-title":"Proc HOT Chip Symp"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SC41405.2020.00062"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/10311055\/10227739.pdf?arnumber=10227739","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,12,11]],"date-time":"2023-12-11T19:54:58Z","timestamp":1702324498000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10227739\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,12]]},"references-count":30,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tc.2023.3307796","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,12]]}}}