{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T14:33:38Z","timestamp":1775745218183,"version":"3.50.1"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2024,2]]},"DOI":"10.1109\/tc.2023.3337308","type":"journal-article","created":{"date-parts":[[2023,12,1]],"date-time":"2023-12-01T18:19:03Z","timestamp":1701454743000},"page":"548-559","source":"Crossref","is-referenced-by-count":5,"title":["Wrong-Path-Aware Entangling Instruction Prefetcher"],"prefix":"10.1109","volume":"73","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5757-1064","authenticated-orcid":false,"given":"Alberto","family":"Ros","sequence":"first","affiliation":[{"name":"Computer Engineering Department, University of Murcia, Murcia, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8642-2447","authenticated-orcid":false,"given":"Alexandra","family":"Jimborean","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, University of Murcia, Murcia, Spain"}]}],"member":"263","reference":[{"key":"ref1","article-title":"McPAT 1.3.","year":"2023"},{"key":"ref2","article-title":"The 1st championship value prediction (CVP-1).","year":"2023"},{"key":"ref3","article-title":"The 1st instruction prefetching championship (IPC1).","year":"2023"},{"key":"ref4","article-title":"A look at the AMD Zen 2 core.","year":"2023"},{"key":"ref5","article-title":"PCACTI.","year":"2023"},{"key":"ref6","article-title":"AMDs Zen 4 part 1: Frontend and execution engine.","year":"2023"},{"key":"ref7","year":"2020","journal-title":"Software Optimization Guide for AMD EPYC\u2122 7003 Processors"},{"key":"ref8","article-title":"MANA: Microarchitecting an instruction prefetcher","volume-title":"Proc. 1st Instruction Prefetching Championship (IPC1)","author":"Ansari","year":"2020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00017"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.38"},{"key":"ref11","first-page":"462","article-title":"AsmDB: Understanding and mitigating front-end stalls in warehouse-scale computers","volume-title":"Proc. 46th Int. Symp. Comput. Archit. (ISCA)","author":"Ayers","year":"2019"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PCCC.1999.749422"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC59245.2023.00027"},{"key":"ref14","first-page":"152","article-title":"Proactive instruction fetch","volume-title":"Proc. 44th Int. Symp. Microarchit. (MICRO)","author":"Ferdman","year":"2011"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771774"},{"key":"ref16","article-title":"The championship simulator: Architectural simulation for education and competition","author":"Gober","year":"2022"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00015"},{"key":"ref18","article-title":"Intel\u00ae 64 and ia-32 architectures optimization reference manual.","volume-title":"Intel.","year":"2023"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS51385.2021.00034"},{"key":"ref20","first-page":"272","article-title":"SHIFT: Shared history instruction fetch for lean-core server processors","volume-title":"Proc. 46th Int. Symp. Microarchit. (MICRO)","author":"Kaynak","year":"2013"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830785"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00024"},{"key":"ref23","first-page":"260","article-title":"RDIP: Return-address-stack directed instruction prefetching","volume-title":"Proc. 46th Int. Symp. Microarchit. (MICRO)","author":"Kolli","year":"2013"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173178"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.53"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658626"},{"key":"ref27","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","volume-title":"Proc. 42nd Int. Symp. Microarchit. (MICRO)","author":"Li","year":"2009"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105405"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054951"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00059"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566459"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176264"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765954"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809439"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/12.919279"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00017"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70742"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232985"},{"key":"ref39","article-title":"A 64-Kbytes ITTAGE indirect branch predictor","volume-title":"Proc. 2nd JILP Workshop Comput. Archit. Competitions (JWAC), Championship Branch Prediction","author":"Seznec","year":"2011"},{"key":"ref40","article-title":"TAGE-SC-L branch predictors again","volume-title":"Proc. 5th JILP Workshop Comput. Archit. Competitions (JWAC), Championship Branch Prediction (CBP)","author":"Seznec","year":"2016"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480046"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903271"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/1089008.1089011"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697009"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514220"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/10400065\/10337781.pdf?arnumber=10337781","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,18]],"date-time":"2024-01-18T01:07:37Z","timestamp":1705540057000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10337781\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,2]]},"references-count":45,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tc.2023.3337308","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,2]]}}}