{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T09:59:03Z","timestamp":1740131943903,"version":"3.37.3"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2024,5,1]],"date-time":"2024-05-01T00:00:00Z","timestamp":1714521600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,5,1]],"date-time":"2024-05-01T00:00:00Z","timestamp":1714521600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,1]],"date-time":"2024-05-01T00:00:00Z","timestamp":1714521600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2024,5]]},"DOI":"10.1109\/tc.2024.3371773","type":"journal-article","created":{"date-parts":[[2024,2,29]],"date-time":"2024-02-29T18:53:20Z","timestamp":1709232800000},"page":"1341-1356","source":"Crossref","is-referenced-by-count":0,"title":["On Key\u2013Value Sort With Active Compute Memory"],"prefix":"10.1109","volume":"73","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8799-5773","authenticated-orcid":false,"given":"Pouya","family":"Esmaili-Dokht","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-3187-2321","authenticated-orcid":false,"given":"Miquel","family":"Guiot","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9334-3330","authenticated-orcid":false,"given":"Petar","family":"Radojkovi\u0107","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0417-3430","authenticated-orcid":false,"given":"Xavier","family":"Martorell","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5146-103X","authenticated-orcid":false,"given":"Eduard","family":"Ayguad\u00e9","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7489-4727","authenticated-orcid":false,"given":"Jesus","family":"Labarta","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-6261-8329","authenticated-orcid":false,"given":"Jason","family":"Adlard","sequence":"additional","affiliation":[{"name":"Micron Technology, Munich, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9601-1462","authenticated-orcid":false,"given":"Paolo","family":"Amato","sequence":"additional","affiliation":[{"name":"Micron Technology, Vimercate, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1794-0982","authenticated-orcid":false,"given":"Marco","family":"Sforzin","sequence":"additional","affiliation":[{"name":"Micron Technology, Vimercate, Italy"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6345-1_8"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/22.643832"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/92.845903"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/70.744603"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CISP.2009.5302455"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357143"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03869-3_41"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3075564.3078885"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.14778\/3368289.3368298"},{"key":"ref10","first-page":"1","article-title":"Sort vs. hash join revisited for near-memory execution","volume-title":"Proc. 5th Workshop Archit. Syst. Big Data (ASBD)","author":"Mirzadeh","year":"2015"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3386263.3407581"},{"year":"2024","key":"ref12","article-title":"ZSim+DRAMsim3 simulation infrastructure for process-in-memory"},{"volume-title":"Introduction to Algorithms","year":"2009","author":"Cormen","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IGSC54211.2021.9651614"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365862"},{"key":"ref16","first-page":"1243","article-title":"Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic","volume-title":"Proc. Des., Automat. Test Eur. Conf. Exhib. (DATE)","author":"Lee","year":"2016"},{"article-title":"Transistor density","volume-title":"IEEE Spectrum","year":"2022","key":"ref17"},{"year":"2019","key":"ref18","article-title":"TSMC announces 6-nanometer process"},{"key":"ref19","first-page":"1","article-title":"A large scale analysis of hundreds of in-memory cache clusters at Twitter","volume-title":"Proc. 14th USENIX Symp. Operating Syst. Des. Implementation (OSDI)","author":"Yang","year":"2020"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.2973991"},{"year":"2018","key":"ref21","article-title":"TN-40-07: Calculating memory power for DDR4 SDRAM"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00030"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2425248.2425252"},{"volume-title":"IBM Power Performance Report","year":"2023","key":"ref25"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3169434"},{"volume-title":"Processing in Memory: The Tipping Point","year":"2021","author":"Radojkovi\u0107","key":"ref27"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.3211117"},{"key":"ref29","first-page":"185","article-title":"RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization","volume-title":"Proc. 46th Annu. IEEE\/ACM Int. Symp. Microarchit. (MICRO)","author":"Seshadr","year":"2013"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1145\/3123939.3124544","article-title":"Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology","volume-title":"Proc. 50th Annu. IEEE\/ACM Int. Symp. Microarchit.","author":"Seshadri","year":"2017"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"ref32","first-page":"288","article-title":"DRISA: A DRAM-based reconfigurable in-situ accelerator","volume-title":"Proc. 50th Annu. IEEE\/ACM Int. Symp. Microarchit. (MICRO)","author":"Li","year":"2017"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00017"},{"key":"ref34","first-page":"1","article-title":"An overview of microns automata processor","volume-title":"Proc. 11th IEEE\/ACM\/IFIP Int. Conf. Hardware\/Softw. Codes. Syst. Synthesis (CODES)","author":"Wang","year":"2016"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00040"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00051"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00055"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00071"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480133"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3097700"},{"volume-title":"Computational Memory Solution for Data-Centric Computing System","year":"2021","author":"hynix","key":"ref41"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00070"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480090"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2873579"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3337821.3337855"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/10494819\/10454132.pdf?arnumber=10454132","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,9]],"date-time":"2024-04-09T05:10:06Z","timestamp":1712639406000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10454132\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5]]},"references-count":45,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tc.2024.3371773","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2024,5]]}}}