{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,22]],"date-time":"2026-07-22T16:28:32Z","timestamp":1784737712730,"version":"3.55.0"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T00:00:00Z","timestamp":1719792000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T00:00:00Z","timestamp":1719792000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T00:00:00Z","timestamp":1719792000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T00:00:00Z","timestamp":1719792000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"NSF","award":["CNS-1815959"],"award-info":[{"award-number":["CNS-1815959"]}]},{"name":"NSF","award":["CPS-2038923"],"award-info":[{"award-number":["CPS-2038923"]}]},{"name":"NSA Science of Security","award":["H98230-18-D-0009"],"award-info":[{"award-number":["H98230-18-D-0009"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2024,7]]},"DOI":"10.1109\/tc.2024.3386059","type":"journal-article","created":{"date-parts":[[2024,4,8]],"date-time":"2024-04-08T20:48:40Z","timestamp":1712609320000},"page":"1753-1766","source":"Crossref","is-referenced-by-count":10,"title":["Analysis and Mitigation of Shared Resource Contention on Heterogeneous Multicore: An Industrial Case Study"],"prefix":"10.1109","volume":"73","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1452-3289","authenticated-orcid":false,"given":"Michael","family":"Bechtel","sequence":"first","affiliation":[{"name":"University of Kansas, Lawrence, KS, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8515-2622","authenticated-orcid":false,"given":"Heechul","family":"Yun","sequence":"additional","affiliation":[{"name":"University of Kansas, Lawrence, KS, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474015"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2019.00020"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.4230\/LIPIcs.ECRTS.2022.1"},{"key":"ref5","year":"2020","journal-title":"ARM Architecture Reference Manual Supplement: Memory System Resource Partitioning and Monitoring (MPAM)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3108044"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS58335.2023.00023"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2018.00011"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2019.00037"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1177\/0278364915620033"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TRO.2021.3075644"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-10605-2_54"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA58653.2023.00014"},{"key":"ref14","first-page":"1","article-title":"Deterministic memory abstraction and supporting multicore system architecture","volume-title":"Proc. Euromicro Conf. Real-Time Syst.","author":"Farshchi","year":"2018"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/LRA.2021.3058069"},{"key":"ref16","article-title":"HopeNet-Lite","year":"2023"},{"key":"ref17","article-title":"rosbag2","year":"2023"},{"key":"ref18","article-title":"Intel\u00ae Resource Director Technology (Intel\u00ae RDT) framework","year":"2022"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS48715.2020.000-6"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/11796435_37"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2013.19"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-017-9272-9"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IROS47612.2022.9981275"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS55097.2022.00028"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3323212"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531078"},{"key":"ref27","first-page":"1","article-title":"Memory performance attacks: Denial of memory service in multi-core systems","volume-title":"Proc. USENIX Secur. Symp.","author":"Moscibroda","year":"2007"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TRO.2015.2463671"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TRO.2017.2705103"},{"key":"ref30","year":"2019","journal-title":"Tegra X1 Mobile Processor Technical Reference Manual (Revision 1.3p)"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS48715.2020.00006"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CVPRW.2018.00281"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS54340.2022.00019"},{"key":"ref35","first-page":"1","article-title":"Memory latency distribution-driven regulation for temporal isolation in MPSoCs","volume-title":"Proc. Euromicro Conf. Real-Time Syst.","author":"Saeed","year":"2023"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3534879.3534882"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS49844.2020.00039"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"ref39","first-page":"33","article-title":"Analyzing performance vulnerability due to resource denial of service attack on chip multiprocessors","volume-title":"Proc. Workshop Chip Multiprocessor Memory Syst. Interconnects","author":"Woo","year":"2007"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2019.00036"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS55097.2022.00040"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925999"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531079"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3202720"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS58335.2023.00026"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/12\/10552674\/10494679-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/10552674\/10494679.pdf?arnumber=10494679","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,25]],"date-time":"2024-06-25T19:38:42Z","timestamp":1719344322000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10494679\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7]]},"references-count":44,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tc.2024.3386059","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,7]]}}}