{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,27]],"date-time":"2026-06-27T15:42:51Z","timestamp":1782574971718,"version":"3.54.5"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"European Union&#x2019;s Chips Joint Undertaking (Chips JU) program","award":["101112274 (ISOLDE)"],"award-info":[{"award-number":["101112274 (ISOLDE)"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2025,6]]},"DOI":"10.1109\/tc.2025.3551936","type":"journal-article","created":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T17:33:14Z","timestamp":1742232794000},"page":"2087-2100","source":"Crossref","is-referenced-by-count":5,"title":["An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research"],"prefix":"10.1109","volume":"74","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9951-062X","authenticated-orcid":false,"given":"Davide","family":"Zoni","sequence":"first","affiliation":[{"name":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0254-3933","authenticated-orcid":false,"given":"Andrea","family":"Galimberti","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-9430-7699","authenticated-orcid":false,"given":"Davide","family":"Galli","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2924045"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3456629"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3124761"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MSEC.2023.3251954"},{"issue":"2","key":"ref5","first-page":"123","article-title":"Hardware Masking, Revisited","volume-title":"IACR Trans. Cryptographic Hardware Embedded Syst.","volume":"2018","author":"Cnudde","year":"2018"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-01957-9_30"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36400-5_3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546758"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD63220.2024.00027"},{"issue":"2","key":"ref12","first-page":"107","article-title":"Non-profiled deep learning-based side-channel attacks with sensitivity analysis","volume-title":"IACR Trans. Cryptogr. Hardware Embedded Syst.","volume":"2019","author":"Timon","year":"2019"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2019.i3.148-179"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2024.3477997"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2996366.2996426"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228376"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS61496.2024.10848741"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2926389"},{"key":"ref19","article-title":"The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1","author":"Waterman","year":"2016"},{"key":"ref20","article-title":"PULPino: A small single-core RISC-V SoC","volume-title":"Proc. 3rd RISCV Workshop","author":"Traber","year":"2016"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2018.8445101"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2912307"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2022.3189390"},{"key":"ref24","volume-title":"DS00004248C - PolarFire SoC Datasheet","year":"2024"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415753"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2020.2996616"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD63220.2024.00108"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.11"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/SCC49971.2021.00010"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD53106.2021.00071"},{"key":"ref34","article-title":"ot-sca - side-channel analysis and fault injection setup for OpenTitan","year":"2024"},{"key":"ref35","article-title":"CW308T-FE310","year":"2020"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2430320"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-019-00220-8"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea9010009"},{"key":"ref39","article-title":"An FPU design template to optimize the accuracy-efficiency-area trade-off","volume-title":"Sustain. Comput.: Inform. Syst.","volume":"29","author":"Zoni","year":"2021"},{"key":"ref40","article-title":"Cost-effective fixed-point hardware support for RISC-V embedded systems","volume-title":"J. Syst. Archit.","volume":"126","author":"Zoni","year":"2022"},{"key":"ref41","article-title":"Design-time methodology for optimizing mixed-precision CPU architectures on FPGA","volume-title":"J. Syst. Archit.","volume":"155","author":"Denisov","year":"2024"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-15074-6_20"},{"key":"ref43","article-title":"NISTIR 8413, Status Report on the 3rd Round of the NIST Post-Quantum Cryptography Standardization Process"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744859"},{"key":"ref45","article-title":"TLS\/SSL and crypto library","year":"2024"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/12\/10994769\/10929027.pdf?arnumber=10929027","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,12]],"date-time":"2025-05-12T17:43:39Z","timestamp":1747071819000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10929027\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6]]},"references-count":45,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tc.2025.3551936","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,6]]}}}