{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,29]],"date-time":"2025-11-29T08:04:21Z","timestamp":1764403461530,"version":"3.41.2"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2025,8,1]],"date-time":"2025-08-01T00:00:00Z","timestamp":1754006400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100011033","name":"Agencia Estatal de Investigación","doi-asserted-by":"publisher","award":["PID2022-136454NB-C22\/AEI\/10.13039\/501100011033"],"award-info":[{"award-number":["PID2022-136454NB-C22\/AEI\/10.13039\/501100011033"]}],"id":[{"id":"10.13039\/501100011033","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Spanish Ministerio de Ciencia e Innovación and European ERDF","award":["PID2021-123627OB-C51","TED2021-130233B-C32"],"award-info":[{"award-number":["PID2021-123627OB-C51","TED2021-130233B-C32"]}]},{"name":"European Union-NextGenerationE","award":["PDC2023-145851-00\/MCIN\/AEI\/10.13039\/501100011033"],"award-info":[{"award-number":["PDC2023-145851-00\/MCIN\/AEI\/10.13039\/501100011033"]}]},{"name":"Department of Science, University, and Knowledge Society, Government of Aragon","award":["gaZ: T58_23R research group"],"award-info":[{"award-number":["gaZ: T58_23R research group"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2025,8]]},"DOI":"10.1109\/tc.2025.3575909","type":"journal-article","created":{"date-parts":[[2025,6,3]],"date-time":"2025-06-03T13:50:11Z","timestamp":1748958611000},"page":"2812-2826","source":"Crossref","is-referenced-by-count":1,"title":["Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches"],"prefix":"10.1109","volume":"74","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0824-5833","authenticated-orcid":false,"given":"Alejandro","family":"Valero","sequence":"first","affiliation":[{"name":"Department of Computer Science and Systems Engineering, Aragon Institute for Engineering Research (I3A), Universidad de Zaragoza, Zaragoza, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9466-2395","authenticated-orcid":false,"given":"Vicente","family":"Lorente","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2426-4134","authenticated-orcid":false,"given":"Salvador","family":"Petit","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8630-4846","authenticated-orcid":false,"given":"Julio","family":"Sahuquillo","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"2006","key":"ref1","article-title":"SPEC CPU\u00ae 2006 benchmark (Retired: January 2018)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1126\/science.1108813"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2975719"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297309"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2537400"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2019.00037"},{"key":"ref7","first-page":"230","article-title":"Low-current perpendicular domain wall motion cell for scalable high-speed MRAM","volume-title":"Proc. IEEE Symp. VLSI Technol.","author":"Fukami","year":"2009"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744800"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3161198"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116245"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3372489"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012266"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2016.7753563"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/NVMSA.2015.7304358"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2019.00016"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea7030023"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2437283"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2391185"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3117439"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2009.5354890"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1126\/science.1145799"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0838"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2021.102145"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627651"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2360545"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3524059.3532383"},{"article-title":"CACTI 5.1","year":"2008","author":"Thoziyoor","key":"ref27"},{"key":"ref28","first-page":"335","article-title":"Multi2Sim: A simulation framework for CPU-GPU computing","volume-title":"Proc. 21st Int. Conf. Parallel Archit. Compilation Techn.","author":"Ubal","year":"2012"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333707"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2506581"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.365"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2723165"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2866932"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2016.2536020"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059042"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7058988"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750388"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357097"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/12\/11077790\/11022726.pdf?arnumber=11022726","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,11]],"date-time":"2025-07-11T17:43:43Z","timestamp":1752255823000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11022726\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8]]},"references-count":38,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tc.2025.3575909","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2025,8]]}}}