{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T06:00:51Z","timestamp":1781157651632,"version":"3.54.1"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002858","name":"China Postdoctoral Science Foundation","doi-asserted-by":"crossref","award":["2025M781480"],"award-info":[{"award-number":["2025M781480"]}],"id":[{"id":"10.13039\/501100002858","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Major Key Project of PCL","award":["PCL2023A03"],"award-info":[{"award-number":["PCL2023A03"]}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["U24B20143"],"award-info":[{"award-number":["U24B20143"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["U22B2021"],"award-info":[{"award-number":["U22B2021"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"NSF of Fujian Province","award":["2024J09045"],"award-info":[{"award-number":["2024J09045"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2026,7]]},"DOI":"10.1109\/tc.2026.3688680","type":"journal-article","created":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T19:47:34Z","timestamp":1777492054000},"page":"2548-2562","source":"Crossref","is-referenced-by-count":0,"title":["Bounded Dynamic Level Maintenance for Efficient Logic Optimization"],"prefix":"10.1109","volume":"75","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-8205-4564","authenticated-orcid":false,"given":"Junfeng","family":"Liu","sequence":"first","affiliation":[{"name":"Department of Optoelectronic Information and Optical Fiber Communication, Pengcheng Laboratory, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4906-7049","authenticated-orcid":false,"given":"Qinghua","family":"Zhao","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligence and Big Data, Hefei University, Hefei, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-7525-9375","authenticated-orcid":false,"given":"Liwei","family":"Ni","sequence":"additional","affiliation":[{"name":"Department of Optoelectronic Information and Optical Fiber Communication, Pengcheng Laboratory, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-4222-8510","authenticated-orcid":false,"given":"Jingren","family":"Wang","sequence":"additional","affiliation":[{"name":"Microelectronics Thrust, Hong Kong University of Science and Technology (Guangzhou), Guangzhou, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4045-6806","authenticated-orcid":false,"given":"Biwei","family":"Xie","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7145-9391","authenticated-orcid":false,"given":"Xingquan","family":"Li","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6406-4810","authenticated-orcid":false,"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4050-0443","authenticated-orcid":false,"given":"Shuai","family":"Ma","sequence":"additional","affiliation":[{"name":"SKLCCSE Lab, Beihang University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","article-title":"IWLS 2005 benchmarks","volume-title":"Proc. Int. Workshop Log. Synthesis (IWLS)","volume":"9","author":"Albrecht","year":"2005"},{"key":"ref2","article-title":"The EPFL combinational benchmark suite","volume-title":"Proc. Int. Workshop Log. Synth. (IWLS)","author":"Amar\u00fa","year":"2015"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927194"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2506566"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342108"},{"key":"ref6","first-page":"7225","article-title":"A graph enhanced symbolic discovery framework for efficient logic optimization","volume-title":"Proc. Int. Conf. Learn. Represent. (ICLR)","author":"Bai","year":"2025"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45749-6_17"},{"key":"ref8","first-page":"15","article-title":"Scalable logic synthesis using a simple circuit structure","volume-title":"Proc. IEEE\/ACM Int. Workshop Logic Synth. (IWLS)","volume":"6","author":"Brayton","year":"2006"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS58744.2024.10558523"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247905"},{"key":"ref13","volume-title":"Introduction to Algorithms","author":"Cormen","year":"2022"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3500930"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3448016.3452796"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s10601-005-0554-9"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3251741"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323902"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473983"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530462"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-025-4300-z"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3524463"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD58817.2023.00059"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3429079"},{"key":"ref25","volume-title":"Synthesis and Optimization of Digital Circuits","author":"Micheli","year":"1994"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"ref27","first-page":"79","article-title":"A batch algorithm for maintaining a topological order","volume":"102","author":"Pearce","year":"2010","journal-title":"Australasian Comput. Sci. Conf."},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240861"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.240"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(95)00079-8"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715185"},{"key":"ref32","article-title":"SIS: A System for Sequential Circuit Synthesis","author":"Sentovich","year":"1992"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6155-2"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3434464"},{"key":"ref35","article-title":"A circuit domain generalization framework for efficient logic synthesis in chip design","volume-title":"Proc. Int. Conf. Mach. Learn. (ICML)","author":"Wang","year":"2024"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2772854"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/12\/11557416\/11499441.pdf?arnumber=11499441","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T05:35:19Z","timestamp":1781156119000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11499441\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7]]},"references-count":36,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tc.2026.3688680","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,7]]}}}