{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,22]],"date-time":"2024-06-22T04:30:12Z","timestamp":1719030612519},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[1985,7,1]],"date-time":"1985-07-01T00:00:00Z","timestamp":489024000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[1985,7]]},"DOI":"10.1109\/tcad.1985.1270114","type":"journal-article","created":{"date-parts":[[2004,4,28]],"date-time":"2004-04-28T20:28:59Z","timestamp":1083184139000},"page":"189-197","source":"Crossref","is-referenced-by-count":19,"title":["Routing Region Definition and Ordering Scheme for Building-Block Layout"],"prefix":"10.1109","volume":"4","author":[{"family":"Wei-Ming Dai","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Asano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.S.","family":"Kuh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref3b","first-page":"37","year":"1983","journal-title":"VLSI 83"},{"key":"ref3a","author":"chen","year":"1983","journal-title":"The Berkeley building block layout system for VLSI design"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1982.1269993"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/800263.809184"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SFCS.1984.715940"},{"key":"ref12","first-page":"260","article-title":"A channel router having layer assignment capability for arbitrary-sized rectangular building blocks","author":"ishii","year":"1982","journal-title":"Proc Int Conf on Computers and Communications"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1983.1270047"},{"key":"ref14","first-page":"658","article-title":"ROBIN: A building block LSI routing program","author":"kani","year":"1976","journal-title":"Proc Int Symp on Circuits and Systems"},{"key":"ref15","first-page":"119","article-title":"A routing method of building block LSI","author":"kawanishi","year":"1973","journal-title":"Rec 7th Asilomar Conf on Circuits Systems and Computers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1983.1270046"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1961.5219222"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"1072","DOI":"10.1109\/TC.1984.1676388","article-title":"Computational geometry: A survey","volume":"c 33","author":"lee","year":"1984","journal-title":"IEEE Trans Comput"},{"key":"ref19","first-page":"647","article-title":"Minimum partitioning of rectilinear regions","volume":"24","author":"ohtsuki","year":"1983","journal-title":"Trans Information Processing Society of Japan"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270096"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1981.1585451"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1983.1585643"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/800158.805069"},{"key":"ref29","first-page":"453","article-title":"FLOORPLANNING, A new placement and routing strategy","author":"verheyen","year":"1984","journal-title":"Proc Int Symp on Circuits and Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/800146.804843"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/800260.809014"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585584"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(83)90004-4"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1981.1585366"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.1674914"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/800263.809216"},{"key":"ref22","first-page":"482","article-title":"Routing algorithm for hierarchical IC layout","author":"preas","year":"1979","journal-title":"Proc Int Symp on Circuits and Systems"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1984.1585789"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585541"},{"key":"ref23","first-page":"143","author":"rivest","year":"1981","journal-title":"VLSI Systems and Computations"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1981.12167"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585533"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/28433\/01270114.pdf?arnumber=1270114","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T15:39:42Z","timestamp":1638200382000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1270114\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1985,7]]},"references-count":31,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1985,7]]}},"URL":"https:\/\/doi.org\/10.1109\/tcad.1985.1270114","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[1985,7]]}}}