{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:02:50Z","timestamp":1742385770879},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[1986,1,1]],"date-time":"1986-01-01T00:00:00Z","timestamp":504921600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[1986,1]]},"DOI":"10.1109\/tcad.1986.1270177","type":"journal-article","created":{"date-parts":[[2004,4,28]],"date-time":"2004-04-28T20:28:59Z","timestamp":1083184139000},"page":"52-65","source":"Crossref","is-referenced-by-count":40,"title":["Stochastic Models for Wireability Analysis of Gate Arrays"],"prefix":"10.1109","volume":"5","author":[{"given":"S.","family":"Sastry","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.C.","family":"Parker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1981.1084958"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675882"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"537","DOI":"10.1109\/T-C.1973.223759","article-title":"how big should a printed circuit board be?","volume":"c 22","author":"sutherland","year":"1973","journal-title":"IEEE Transactions on Computers"},{"key":"ref6","author":"mann","year":"1974","journal-title":"Methods for Statistical Analysis of Reliability and Life Data"},{"key":"ref5","first-page":"117","author":"heller","year":"1978","journal-title":"Design Automation and Fault-Tolerant Computing"},{"key":"ref8","author":"sastry","year":"1983","journal-title":"Wiring space estimation of master slice ICs"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5008919"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.252.0152"},{"key":"ref9","author":"sastry","year":"1985","journal-title":"Wireability analysis of Integrated circuits"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084635"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/28435\/01270177.pdf?arnumber=1270177","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T15:39:43Z","timestamp":1638200383000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1270177\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1986,1]]},"references-count":10,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1986,1]]}},"URL":"https:\/\/doi.org\/10.1109\/tcad.1986.1270177","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[1986,1]]}}}