{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T15:25:41Z","timestamp":1764602741037},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[1986,10,1]],"date-time":"1986-10-01T00:00:00Z","timestamp":528508800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[1986,10]]},"DOI":"10.1109\/tcad.1986.1270229","type":"journal-article","created":{"date-parts":[[2004,4,29]],"date-time":"2004-04-29T00:28:59Z","timestamp":1083198539000},"page":"582-596","source":"Crossref","is-referenced-by-count":62,"title":["Synthesis and Optimization of Multilevel Logic under Timing Constraints"],"prefix":"10.1109","volume":"5","author":[{"given":"K.","family":"Bartlett","sequence":"first","affiliation":[]},{"given":"W.","family":"Cohen","sequence":"additional","affiliation":[]},{"given":"A.","family":"De Geus","sequence":"additional","affiliation":[]},{"given":"G.","family":"Hachtel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294719"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1983.1270033"},{"key":"ref12","author":"demicheli","year":"1985","journal-title":"Advances in Computer Engineering Design"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1982.1269996"},{"key":"ref14","article-title":"A domino CMOS logic synthesis system","author":"hoffman","year":"1985","journal-title":"Proc IEEE Int Symp on Circuits and Systems"},{"key":"ref15","author":"rudell","year":"1986","journal-title":"master's report"},{"key":"ref16","article-title":"An application of multiple-valued logic to a design of masterslice gate arrays","author":"sasao","year":"1982","journal-title":"Proc ISMVL-82"},{"key":"ref17","article-title":"Multilevel logic and minimization","author":"bartlett","year":"1985","journal-title":"Proc IEEE Int Conf on CAD"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-2821-6","author":"brayton","year":"1984","journal-title":"Logic Minimization Algorithms for VLSI Synthesis"},{"key":"ref3","first-page":"49","article-title":"The decomposition and factorization of Boolean expressions","author":"brayton","year":"1982","journal-title":"Proc Int Symp on Circuits and Systems"},{"key":"ref6","first-page":"49","article-title":"Synthesis and optimization of multistage logic","author":"brayton","year":"1984","journal-title":"Proc IEEE Int Conf on Computer Design"},{"key":"ref5","article-title":"Automated implementation of switching functions as dynamic CMOS circuits","author":"brayton","year":"1984","journal-title":"Proc IEEE Custom Integrated Circuits Conf"},{"key":"ref8","first-page":"873","article-title":"Impact of metarules in a rule based expert system for gate level optimization","author":"cohen","year":"1985","journal-title":"Proc IEEE Int Symp on Circuits and Systems"},{"key":"ref7","author":"brayton","year":"1985","journal-title":"private communication"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1986.1270229"},{"key":"ref1","article-title":"Library specific optimization of multilevel combinational logic","author":"bartlett","year":"1985","journal-title":"Proc IEEE Int Conf on Computer Design"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1147\/rd.285.0537"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/28438\/01270229.pdf?arnumber=1270229","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:39:44Z","timestamp":1638218384000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1270229\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1986,10]]},"references-count":17,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1986,10]]}},"URL":"https:\/\/doi.org\/10.1109\/tcad.1986.1270229","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[1986,10]]}}}