{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:50:05Z","timestamp":1761580205608},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[1987,3,1]],"date-time":"1987-03-01T00:00:00Z","timestamp":541555200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[1987,3]]},"DOI":"10.1109\/tcad.1987.1270271","type":"journal-article","created":{"date-parts":[[2004,4,28]],"date-time":"2004-04-28T20:28:59Z","timestamp":1083184139000},"page":"270-281","source":"Crossref","is-referenced-by-count":342,"title":["CMOS Circuit Speed and Buffer Optimization"],"prefix":"10.1109","volume":"6","author":[{"given":"N.","family":"Hedenstierna","sequence":"first","affiliation":[]},{"given":"K.O.","family":"Jeppson","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052218"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1983.1270030"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(83)90160-0"},{"key":"ref6","first-page":"627","article-title":"Switching response of complementary-symmetry MOS transistor logic circuits","volume":"25","author":"burns","year":"1964","journal-title":"RCA Rev"},{"key":"ref11","year":"1985","journal-title":"Portable CMOS Design Rules for the Swedish Universities"},{"key":"ref5","author":"mead","year":"1980","journal-title":"Introduction to VLSI-Systems"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052103"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270130"},{"key":"ref7","article-title":"Event-driven simulation of general CMOS circuits with delay modeling","author":"bobev","year":"0","journal-title":"IEEE Trans Computer-Aided Design"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1980.1051371"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052168"},{"key":"ref1","first-page":"4","author":"elmasry","year":"1981","journal-title":"Digital MOS Integrated Circuits"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/28440\/01270271.pdf?arnumber=1270271","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T15:39:45Z","timestamp":1638200385000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1270271\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,3]]},"references-count":12,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1987,3]]}},"URL":"https:\/\/doi.org\/10.1109\/tcad.1987.1270271","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[1987,3]]}}}