{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,15]],"date-time":"2025-04-15T06:11:54Z","timestamp":1744697514740},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[1987,7,1]],"date-time":"1987-07-01T00:00:00Z","timestamp":552096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[1987,7]]},"DOI":"10.1109\/tcad.1987.1270308","type":"journal-article","created":{"date-parts":[[2004,4,29]],"date-time":"2004-04-29T00:28:59Z","timestamp":1083198539000},"page":"601-617","source":"Crossref","is-referenced-by-count":80,"title":["HSS--A High-Speed Simulator"],"prefix":"10.1109","volume":"6","author":[{"given":"Z.","family":"Barzilai","sequence":"first","affiliation":[]},{"given":"J.L.","family":"Carter","sequence":"additional","affiliation":[]},{"given":"B.K.","family":"Rosen","sequence":"additional","affiliation":[]},{"given":"J.D.","family":"Rutledge","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","first-page":"779","article-title":"A statistical calculation of fault detection probabilities by fast fault simulation","author":"waicukauski","year":"1985","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref32","doi-asserted-by":"crossref","first-page":"374","DOI":"10.1145\/800139.804558","article-title":"High-speed concurrent fault simulation with vectors and scalars","author":"ulrich","year":"1980","journal-title":"Proc IEEE-ACM Design Automation Conf"},{"key":"ref31","first-page":"74","article-title":"A simulation engine in the design environment?Part 2: Fault simulation methodology and results","volume":"5","author":"smith","year":"1984","journal-title":"VLSI Design"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.5009315"},{"key":"ref35","first-page":"19","article-title":"Random patterns within a structured sequential logic design","author":"williams","year":"1977","journal-title":"Proc Semiconductor Test Conf"},{"key":"ref34","first-page":"20","article-title":"Fault simulation for structured VLSI","volume":"6","author":"waicukauski","year":"1985","journal-title":"VLSI Systems Design"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-95424-5"},{"key":"ref11","first-page":"695","article-title":"Accelerated ATPG and fault grading via testability analysis","author":"brglez","year":"1985","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref12","first-page":"683","article-title":"ATPG via random pattern simulation","author":"carter","year":"1985","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223820"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1984.1585766"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1147\/rd.254.0272"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1984.1585768"},{"key":"ref17","first-page":"165","article-title":"A logic design structure for LSI testability","volume":"2","author":"eichelberger","year":"1978","journal-title":"J Design Automat Fault-Tolerant Comput"},{"key":"ref18","first-page":"2","article-title":"Signature analysis: A new digital field service method","volume":"28","author":"frohwerk","year":"1977","journal-title":"Hewlett-Packard J"},{"key":"ref19","first-page":"22","article-title":"Fault simulation techniques for VLSI circuits","volume":"5","author":"goel","year":"1984","journal-title":"VLSI Design"},{"key":"ref28","first-page":"96","article-title":"A simulation engine in the design environment?Part I: Normal simulation methodology and results","volume":"5","author":"rezac","year":"1984","journal-title":"VLSI Design"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1986.1586084"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1147\/rd.273.0237"},{"key":"ref3","first-page":"200","article-title":"Self-testing of multichip logic modules","author":"bardell","year":"1982","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref6","first-page":"722","article-title":"Accurate modeling and efficient simulation of differential CVS circuits","author":"barzilai","year":"1985","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref29","first-page":"710","article-title":"CHIEFS: A concurrent, hierarchical, and extensible fault simulator","author":"rogers","year":"1985","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref5","first-page":"42","article-title":"Fault modeling and simulation of SCVS circuits","author":"barzilai","year":"1984","journal-title":"Proc IEEE Int Conf Computer Design"},{"key":"ref8","first-page":"208","article-title":"Self-testing by polynomial division","author":"bhavsar","year":"1981","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref7","first-page":"89","article-title":"Comparison of AC self-testing procedures","author":"barzilai","year":"1983","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref2","author":"aho","year":"1977","journal-title":"Principles of Compiler Design"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1984.5005647"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1983.1270024"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270276"},{"key":"ref22","first-page":"206","article-title":"DECSIM: A multilevel simulation system for digital design","author":"kearney","year":"1984","journal-title":"Proc IEEE Int Conf Computer Design"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294683"},{"key":"ref24","first-page":"530","article-title":"Modeling and simulation of delay faults in CMOS logic circuits","author":"koeppe","year":"1986","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref23","first-page":"37","article-title":"Built-in logic block observation techniques","author":"koenemann","year":"1979","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref26","first-page":"83","article-title":"On fault simulation techniques","volume":"3","author":"ozguner","year":"1979","journal-title":"J Design Automat Fault-Tolerant Comput"},{"key":"ref25","first-page":"283","article-title":"An LSSD pseudorandom pattern test system","author":"motika","year":"1983","journal-title":"Proc IEEE Int Test Conf"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/28442\/01270308.pdf?arnumber=1270308","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,28]],"date-time":"2023-04-28T14:05:43Z","timestamp":1682690743000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1270308\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,7]]},"references-count":35,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1987,7]]}},"URL":"https:\/\/doi.org\/10.1109\/tcad.1987.1270308","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[1987,7]]}}}